• Physical Design Engineer

    SanDisk (Milpitas, CA)
    …keep our world moving forward. **Job Description** We are looking for an experienced **Digital Physical Design Engineer ** to work whole digital SPR flow from ... REQUIRED: + **Experience:** A minimum of 3 years in Physical design digital RTL to GDS flow....**EDA Tools:** Familiarity with Cadence, Synopsys digital flow include Synthesis , PNR, STA. Calibre physical verification, Redhawk… more
    SanDisk (10/10/25)
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  • Senior Synthesis Flow CAD Engineer

    NVIDIA (Santa Clara, CA)
    …modern software engineering methodologies + Build flows for methodologies incorporating logic/ physical synthesis , design planning, equivalence checking for ... of Python, Perl , Tcl, C/C++ + Knowledge or experience with logic synthesis , physical design , formal equivalence checking. + Proven track record developing… more
    NVIDIA (09/09/25)
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  • Sr. Physical Design Methodology…

    Amazon (Cupertino, CA)
    …massive scale and rapid integration of emergent technologies. We're looking for an ASIC Physical Design Methodology Engineer to help us trail-blaze new ... in EE/CS - 5+ years developing physical design methodology or CAD flows in synthesis ,...languages (Perl, Python, C++) - Solid understanding of ASIC physical design , and methodologies including synthesis more
    Amazon (10/25/25)
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  • Sr. Physical Design Engineer

    Amazon (Cupertino, CA)
    …massive scale and rapid integration of emergent technologies. We're looking for an ASIC Physical Design Engineer to help us trail-blaze new technologies and ... tradeoffs for physical design closure - Drive IO/Core block physical implementation through synthesis , floor planning, bus / pin planning, place and… more
    Amazon (09/02/25)
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  • Physical Design Methodology…

    Amazon (Cupertino, CA)
    …of machine learning and AI services for our customers' businesses. We are seeking experienced Physical Design Engineer to build the next generation of our ... ASIC physical design , physical design flows, and methodologies including synthesis , place and route, STA, formal verification. - Proven track record… more
    Amazon (09/02/25)
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  • Physical Design Engineer

    SpaceX (Sunnyvale, CA)
    Physical Design Engineer (Silicon Engineering) Sunnyvale, CA Apply SpaceX was founded under the belief that a future where humanity is out exploring the ... the ultimate goal of enabling human life on Mars. PHYSICAL DESIGN ENGINEER (SILICON ENGINEERING)...capabilities of the Starlink network. RESPONSIBILITIES: + Perform partition synthesis and physical implementation steps (eg … more
    SpaceX (10/07/25)
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  • Senior Logic Design Engineer

    NVIDIA (Santa Clara, CA)
    We are now looking for a Logic Design Engineer with Physical Design background! As a member of our CPU Logic Design Team, you will be responsible for ... on-chip interconnect network and last-level caches , working closely with the physical design team on implementation, synthesis and timing closure as well… more
    NVIDIA (09/10/25)
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  • Senior ASIC Physical Design

    NVIDIA (Santa Clara, CA)
    …human inventiveness and intelligence. We are now looking for a motivated Senior ASIC Physical Design Engineer , Netlisting to join our dynamic and growing ... intelligence. What you'll be doing: + You will drive physical design of high-frequency and low-power CPUs,...including clock domain crossing checks and MTBF analysis, logic synthesis , netlist quality checks, etc. + Help in all… more
    NVIDIA (10/22/25)
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  • Senior CPU Physical Design

    Google (Mountain View, CA)
    Senior CPU Physical Design Engineer , Silicon...+ 5 years of experience with physical design flow such as constraints, synthesis , floor ... and route, clock tree synthesis (CTS), or physical verification. + Experience in one or more sign-off...drive architectural feasibility studies, and identify power-performance-area tradeoffs for physical design closure. + Drive block/IP … more
    Google (10/01/25)
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  • Principal Engineer , VLSI Design

    SanDisk (Milpitas, CA)
    …of digital design in NAND Flash memory, focusing on micro architecture, RTL design , verification, logic synthesis , and timing analysis to deliver a design ... and verification in Verilog, RTL linting, clock domain crossing (CDC) analysis, design integration, synthesis , DFT, timing analysis and closure + Balance … more
    SanDisk (09/11/25)
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