- Google (Sunnyvale, CA)
- …+ 3 years of experience in ASIC physical design flows with emphasis on physical verification convergence and tapeout signoff. + Experience in full chip ... + Work with floorplan and physical design engineers to drive physical verification convergence . + Perform technical physical evaluations of vendors,… more
- Capgemini (San Jose, CA)
- …industry knowledge and cutting-edge technologies in digital and software to support the convergence of the physical and digital worlds. Coupled with the ... _Developer_ **Organization:** _ERD PPL US_ **Title:** _Senior E/E & Semiconductor Engineer - Mixed-Signal Design Verification Engineer_ **Location:** _CA-San… more
- Capgemini (San Francisco, CA)
- …industry knowledge and cutting-edge technologies in digital and software to support the convergence of the physical and digital worlds. Coupled with the ... _Developer_ **Organization:** _ERD PPL US_ **Title:** _Senior E/E & Semiconductor Engineer - Design Verification (DV) Engineer_ **Location:** _CA-San Francisco_… more
- Capgemini (Los Angeles, CA)
- **About the job you're considering** Join Capgemini Engineering as a Verification and Validation Engineer to work on ambitious projects with top professionals. ... industry knowledge and cutting-edge technologies in digital and software to support the convergence of the physical and digital worlds. Coupled with the… more
- NVIDIA (Santa Clara, CA)
- …distribution, Place and Route, Integration and Verification . + Staring knowledge of Physical design with convergence in timing/EM/IR with best PPA + Strong ... background with hierarchical design approach, top-down design, budgeting, timing and physical convergence . + Familiar with various process related design issues… more
- NVIDIA (Santa Clara, CA)
- …Strong background with hierarchical design approach, top-down design, budgeting, timing and physical convergence . + Familiar with various process related design ... human inventiveness and intelligence. NVIDIA is looking for best-in-class Senior Physical Design Methodology Engineer (s) to join our outstanding Networking… more
- Meta (Sunnyvale, CA)
- …place and route, clock tree synthesis, static timing analysis, IR drop, EM, and physical verification in advanced technology nodes. 2. Resolve design and flow ... System on Chip (SoC) and IP for data center applications. **Required Skills:** ASIC Engineer , Physical Design Responsibilities: 1. Develop and own physical … more
- SpaceX (Irvine, CA)
- … verification and timing closure + Work closely with chip architecture, design verification , physical design, DFT, and power teams to achieve tapeout success ... Sr. SOC/ASIC Timing Signoff & Front-End Implementation Engineer (Silicon Engineering) Irvine, CA Apply SpaceX was...+ Full chip and block level timing signoff and convergence through timing ecos on post routed database for… more
- Capgemini (San Jose, CA)
- …industry knowledge and cutting-edge technologies in digital and software to support the convergence of the physical and digital worlds. Coupled with the ... job you're considering:** We are seeking a highly skilled Python Infrastructure Engineer with a strong foundation in Python programming, data structures, and… more
- Capgemini (San Francisco, CA)
- …industry knowledge and cutting-edge technologies in digital and software to support the convergence of the physical and digital worlds. Coupled with the ... **Job Title: RTL Engineer ** **Job Location:** **San Francisco CA** **Job Description**...and other (QC) quality checking like CDC/RDC and basic verification of designs. + Experience supporting SoC designers in… more
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