- Broadcom (San Jose, CA)
- …Sign-In before you apply.** **Job Description:** Broadcom is looking for a senior level STA engineer . In this highly visible role, you will be contributing to ... timing constraints for intricate SoC designs. + Perform static timing analysis ( STA ) using industry-standard tools (eg, PrimeTime, Tempus). + Define and implement… more
- Arrow Electronics (San Jose, CA)
- **Position:** STA Engineer (eInfochips Inc) **Job Description:** **What You'll Be Doing:** + Designing the integrated chips by estimating the die area, floor ... planning, placement of memory, power planning, placement, clock building, routing + Design and development of sign off flows based on product specification, which includes, static timing analysis, IR/EM and physical verification through which design will be… more
- Amazon (Sunnyvale, CA)
- …that is powering the latest generation of Echo devices is looking for a Senior SoC Design- STA Engineer to continue to innovate on behalf of our customers. We are ... development of signoff methodology and corresponding implementation solution * Flow for STA , Crosstalk Delay and Crosstalk Noise analysis for digital ASIC/SoCs. *… more
- Ford Motor Company (Sacramento, CA)
- …We get up every day, roll up our sleeves and build a better world -- together. At Ford, we're all a part of something bigger than ourselves. What will you make today? ... The Supply Chain team adds critical value to the entire organization. You'll help us source the highest quality parts and services from around the globe while ensuring optimal cost and on-time delivery. You'll also contribute to establishing a robust supply… more
- Cadence Design Systems, Inc. (San Jose, CA)
- …on SDC constraints, advanced OCV/SOCV concepts, derates, PBA timing, Distributed and Concurrent STA flows. . Work efficiently with R&D and customer to enable various ... timing analysis & ECO flows including newer advanced technologies. . Performing timing correlation, tool feature benchmarking, constraints validation, spice analysis on various tech nodes and customer designs. . Work on In-design timing ECO optimizations… more
- SanDisk (Milpitas, CA)
- …forward. **Job Description** We are looking for an experienced **Digital Physical Design Engineer ** to work whole digital SPR flow from RTL to GDS, include ... Synthesis, DFT scan insertion, PNR, STA timing analysis, IRdrop power analysis, DRC/LVS verification. Experienced...and analysis timing, routing issue in routeOpt stage, + ** STA timing analysis** + MMMC timing analysis using PT… more
- NVIDIA (Santa Clara, CA)
- …inventiveness and intelligence. We are seeking an innovative Senior Timing Methodology Engineer to help drive sign-off strategies for the world's leading GPUs and ... and validate flows for Prime-Time , Prime-Shield and Tempus STA QoR metrics for sign-off flow, and tool for...std cells and custom IPs. + Develop flows/recommendations on STA sign-off to model deep submicron physical effects aging,… more
- NVIDIA (Santa Clara, CA)
- …and intelligence. We are now looking for a motivated Senior ASIC Test Timing Engineer to join our dynamic and growing team. If you want to challenge yourself ... or MS (or equivalent experience) with 2+ years' experience in Timing and STA + Hands-on experience in full-chip/sub-chip Static Timing Analysis ( STA ) and… more
- Arrow Electronics (San Jose, CA)
- **Position:** Physical Design Engineer (Einfochips Inc) **Job Description:** **What candidate will Be Doing:** + Netlist to-GDSII implementation, including top-level ... simulation, power mesh planning, and full signoff (DRC, LVS, STA , EMIR). + Own and drive PnR execution and...like DDR and PCIe. + Collaborate cross-functionally with RTL, STA , DFT, verification, and packaging teams to ensure smooth… more
- Broadcom (San Jose, CA)
- …Account, please Sign-In before you apply.** **Job Description:** **Principal DFT Engineer ** Broadcom's ASIC Product Division is seeking candidates for a DFT ... metrics. It involves working with the Physical Design & STA team for DFT mode timing closure. The role...and other I/P DFT integration + Working closely with STA and DI Engineers design closure for test +… more
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