• SanDisk (Milpitas, CA)
    …forward. **Job Description** We are looking for an experienced **Digital Physical Design Engineer ** to work whole digital SPR flow from RTL to GDS, include ... Synthesis, DFT scan insertion, PNR, STA timing analysis, IRdrop power analysis, DRC/LVS verification. Experienced...and analysis timing, routing issue in routeOpt stage, + ** STA timing analysis** + MMMC timing analysis using PT… more
    DirectEmployers Association (10/10/25)
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  • STA Engineer

    Broadcom (San Jose, CA)
    …Sign-In before you apply.** **Job Description:** Broadcom is looking for a senior level STA engineer . In this highly visible role, you will be contributing to ... timing constraints for intricate SoC designs. + Perform static timing analysis ( STA ) using industry-standard tools (eg, PrimeTime, Tempus). + Define and implement… more
    Broadcom (10/09/25)
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  • STA Principal Application Engineer

    Cadence Design Systems, Inc. (San Jose, CA)
    …on SDC constraints, advanced OCV/SOCV concepts, derates, PBA timing, Distributed and Concurrent STA flows. . Work efficiently with R&D and customer to enable various ... timing analysis & ECO flows including newer advanced technologies. . Performing timing correlation, tool feature benchmarking, constraints validation, spice analysis on various tech nodes and customer designs. . Work on In-design timing ECO optimizations… more
    Cadence Design Systems, Inc. (11/13/25)
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  • Senior Timing Methodology Engineer

    NVIDIA (Santa Clara, CA)
    …inventiveness and intelligence. We are seeking an innovative Senior Timing Methodology Engineer to help drive sign-off strategies for the world's leading GPUs and ... and validate flows for Prime-Time , Prime-Shield and Tempus STA QoR metrics for sign-off flow, and tool for...std cells and custom IPs. + Develop flows/recommendations on STA sign-off to model deep submicron physical effects aging,… more
    NVIDIA (11/20/25)
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  • Signoff Methodology Engineer - New College…

    NVIDIA (Santa Clara, CA)
    …inventiveness and intelligence. We are seeking an innovative Timing Methodology Engineer to help drive multi-physics sign-off strategies for the world's leading ... and validate flows for Prime-Time , Prime-Shield and Tempus STA QoR metrics for sign-off flow, and tool for...std cells and custom IPs. + Develop flows/recommendations on STA sign-off to model deep submicron physical effects aging,… more
    NVIDIA (11/05/25)
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  • Principal Plan Check Engineer

    City of Santa Monica (Santa Monica, CA)
    Principal Plan Check Engineer Print (https://www.governmentjobs.com/careers/santamonica/jobs/newprint/5151872) Apply  Principal Plan Check Engineer Salary ... construction management work. Plans and coordinates the work activities of assigned sta ?. SUPERVISION Works under the general supervision of the Assistant Building… more
    City of Santa Monica (11/24/25)
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  • Senior ASIC Test Timing Engineer

    NVIDIA (Santa Clara, CA)
    …and intelligence. We are now looking for a motivated Senior ASIC Test Timing Engineer to join our dynamic and growing team. If you want to challenge yourself ... or MS (or equivalent experience) with 2+ years' experience in Timing and STA + Hands-on experience in full-chip/sub-chip Static Timing Analysis ( STA ) and… more
    NVIDIA (10/07/25)
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  • Physical Design Engineer

    MetaOption, LLC (Milpitas, CA)
    Physical Design Engineer - Milpitas, CA We're looking for a hands-on Physical Design Engineer to support complex SoC projects for our client who designs and ... experience. Local candidates are preferred. Key Responsibilities: + Pre-layout STA for feasibility and timing constraint validation + Chip/block-level floorplanning… more
    MetaOption, LLC (11/20/25)
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  • DFT Engineer

    Broadcom (San Jose, CA)
    …Account, please Sign-In before you apply.** **Job Description:** **Principal DFT Engineer ** Broadcom's ASIC Product Division is seeking candidates for a DFT ... metrics. It involves working with the Physical Design & STA team for DFT mode timing closure. The role...and other I/P DFT integration + Working closely with STA and DI Engineers design closure for test +… more
    Broadcom (09/05/25)
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  • Digital Design Engineer

    Meta (Sunnyvale, CA)
    **Summary:** We are looking for a Digital Design Engineer to support our Reality Labs Silicon AI Research team. We build research silicon to demonstrate and ... next generation AI and AR solutions.As a Digital Design Engineer (DDE), you will be a key contributor in...(DV) 3. Support back end physical design (PD) through STA and SDCs 4. Develop system tests in C… more
    Meta (09/09/25)
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