• STA Engineer

    Broadcom (San Jose, CA)
    …please Sign-In before you apply.** **Job Description:** Broadcom is looking for a senior level STA engineer . In this highly visible role you will be working on ... with timing ECO creation and final timing signoff. + Proficiency in using STA tools (eg, PrimeTime, Tempus) and scripting languages (eg, Tcl, Perl). + Proficiency… more
    Broadcom (05/08/25)
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  • Implementation Timing / STA Design…

    Qualcomm (Santa Clara, CA)
    …for skilled engineers to focus on timing constraints development, power analysis, STA , and timing closure for premium-tier chips. This is an excellent opportunity ... to join the Snapdragon implementation team, which is responsible for SoCs in sub-3nm nodes across mobile, AI, and automotive sectors. Candidates should have at least 2 years of experience and be proficient with tools such as Primetime, Fishtail/TCM. Scripting… more
    Qualcomm (04/08/25)
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  • Sr. SOC/ASIC Timing Signoff & Front-End…

    SpaceX (Irvine, CA)
    …computer science + 5+ years of experience working as a synthesis and/or front-end STA engineer PREFERRED SKILLS AND EXPERIENCE: + Experience in ASIC multimode ... deadlines, as needed COMPENSATION & BENEFITS: Pay range: Synthesis and Front-End STA Engineer /Senior: $160,000.00 - $220,000.00/per year Your actual level and… more
    SpaceX (04/15/25)
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  • SOC/ASIC Timing Signoff & Front-End Implementation…

    SpaceX (Irvine, CA)
    …critical deadlines, as needed COMPENSATION & BENEFITS: Pay range: Physical Design STA /Timing Engineer /Level I: $120,000.00 - $145,000.00/per year Physical Design ... SOC/ASIC Timing Signoff & Front-End Implementation Engineer (Silicon Engineering) Irvine, CA Apply SpaceX was... STA /Timing Engineer /Level II: $140,000.00 - $170,000.00/per year Your actual level… more
    SpaceX (04/15/25)
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  • Design Methodology Engineer

    Qualcomm (San Diego, CA)
    … engineer to drive development of advanced methodologies in die-level IR drop, STA , and power. The engineer should be proficient in static timing analysis ... IR drop analysis and optimization is also helpful. The engineer is expected to propose, develop, and validate new...and optimization methodologies for interaction of IR drop and STA ⦁ Develop physical-aware timing and IR drop ECO… more
    Qualcomm (05/01/25)
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  • CPU Physical Design Timing Engineer

    Qualcomm (Folsom, CA)
    …CPU timing closure for Oryon CPU Cores. As a CPU Physical Design Timing Engineer , you will work with microarchitecture and RTL design team to develop timing ... One of your primary responsibilities will lie in coding scripts used with STA native tools and also useful in enabling CPU timing infrastructure and methodology… more
    Qualcomm (03/04/25)
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  • Signoff Static Timing Analysis and Spice CAD…

    Qualcomm (San Diego, CA)
    …developing good-by-construction hierarchical solution, as well as enabling the latest STA features to reduce conservatism in Signoff. **This role's responsibilities ... initiatives for compute and turn-around time reduction. + Correlation of STA tools with spice, version-to-version validation. + Provide solutions to the… more
    Qualcomm (03/04/25)
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  • Senior Timing Methodology Engineer

    NVIDIA (Santa Clara, CA)
    …inventiveness and intelligence. We are seeking an innovative Senior Timing Methodology Engineer to help drive sign-off strategies for the world's leading GPUs and ... and validate flows for Prime-Time , Prime-Shield and Tempus STA QoR metrics for sign-off flow, and tool for...std cells and custom IPs. + Develop flows/recommendations on STA sign-off to model deep submicron physical effects aging,… more
    NVIDIA (04/18/25)
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  • ASIC Implementation Engineer - Timing

    Meta (Sunnyvale, CA)
    …and IP for data center applications. **Required Skills:** ASIC Implementation Engineer - Timing Responsibilities: 1. Develop Timing Constraints for RTL-Synthesis and ... PrimeTime- STA for the blocks and the top-level including SOC....Hierarchical Constraints for Functional & DFT Modes. 4. Perform STA for full chip and Physical partition blocks using… more
    Meta (04/23/25)
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  • Senior ASIC Timing Engineer

    NVIDIA (Santa Clara, CA)
    …human inventiveness and intelligence. We are now looking for a motivated ASIC Timing Engineer to join our dynamic and growing team. If you want to challenge yourself ... or MS (or equivalent experience) with 2 years experience in Timing and STA + Hands-on experience in full-chip/sub-chip Static Timing Analysis ( STA ) and… more
    NVIDIA (03/18/25)
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