- NVIDIA (Santa Clara, CA)
- …+ Micro architect and design next generation clock topologies and modules. + ASIC Clock scheme definition. + Improve Power, Performance, and Area (PPA) of ... NVIDIA Networking Clock design team is looking for experienced top notch ASIC design engineer to work on next generation of NVIDIA Networking chips. We're… more
- NVIDIA (Santa Clara, CA)
- We are now looking for a Senior ASIC Floorplan Design Engineer ! NVIDIA is seeking a talented ASIC Floorplan Engineer to design and implement the ... chip development. + Drive the area review process and collaborate with the ASIC design team to identify area, interconnect and floorplan improvement opportunities +… more
- Qualcomm (San Diego, CA)
- …smarter, connected future for all. As a Qualcomm Design Verification Hardware Engineer , you will plan, design, optimize, verify, and test electronic systems, ... meet performance, security, technology, and feature requirements. As a Design Verification Engineer , you will work with Chip Architects to validate the concepts of… more
- Arrow Electronics (San Jose, CA)
- **Position:** Senior ASIC Design Engineer (eInfochips Inc) **Job Description:** **What candidate will Be Doing:** + Map multi-million gate SoC designs onto ... by a minimum of 10 years of experience in ASIC or a related field, or a Master's Degree...+ **An in-depth knowledge of digital design concepts, including Clock Domain Crossing (CDC), Reset Domain Crossing (RDC).** +… more
- SpaceX (Irvine, CA)
- …Enjoys being challenged and learning new skills COMPENSATION & BENEFITS: Pay range: ASIC Design Engineer / Senior : $160,000.00 - $220,000.00/per year Your ... Sr. ASIC Design Engineer (Silicon Engineering) Irvine,...AND EXPERIENCE: + Ability to solve complex problems including clock domain crossings and power optimization + ASIC… more
- NVIDIA (Santa Clara, CA)
- …design tradeoffs and methodology on next generation CMOS technology. We are looking for a Senior ASIC Timing Engineer to join our dynamic and growing team! ... shift, scan capture, transition faults, BIST, etc. + Knowledge of clocking and clock controls in DFT modes. + Experience in methodology or flow development. NVIDIA… more
- NVIDIA (Santa Clara, CA)
- …work, to amplify human inventiveness and intelligence. We are now looking for a motivated ASIC Physical Design Engineer to join our dynamic and growing team. If ... area, congestions, etc.) and methods/techniques to address those. + Understanding of high-speed clock distribution and planning as well as impact of DFT logic in… more
- Amazon (Cupertino, CA)
- …scale and rapid integration of emergent technologies. We're looking for an ASIC Design Eengineer to help us trail-blaze new technologies and architectures, while ... integrate multiple subsystems into top level SOC, ensure correct clock /reset/functional/DFT signal routing - As a key member of...signal routing - As a key member of the ASIC design team, you will implement and deliver high… more
- NVIDIA (Santa Clara, CA)
- …to amplify human inventiveness and intelligence. We are seeking an innovative senior timing signoff and constraint methodology engineer to develop pioneering ... and formal processes for constraint correctness + Analyze RTL clock constructs to derive clock definitions and...Electrical or Computer Engineering with 4+ years' experience in ASIC Design and Timing. + Expertise in Primetime and… more
- NVIDIA (Santa Clara, CA)
- …work, to amplify human inventiveness and intelligence. We are seeking an innovative Senior Timing Methodology Engineer to help drive sign-off strategies for the ... Electrical or Computer Engineering with 3 years' experience in ASIC Design and Timing. + Good understanding of modeling...of low power design techniques such as multi VT, Clock gating, Power gating, Block Activity Power, and Dynamic… more
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