• Senior ASIC Design

    NVIDIA (Santa Clara, CA)
    We are now looking for a Senior ASIC Design Engineer . NVIDIA is seeking ASIC Design Engineers to implement the world's leading SoC's and GPU's. ... & bus protocols, interconnect networks and/or caches. + Great understanding of ASIC design flow including RTL design , verification, logic synthesis and… more
    NVIDIA (12/09/25)
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  • Senior ASIC Design

    NVIDIA (Santa Clara, CA)
    We are looking for a Senior ASIC Design Engineer to join our Switch Silicon team. As a Design Engineer at NVIDIA, you'll join a group of ... a focus on high bandwidth data paths. + A deep understanding of ASIC design flows including RTL design , verification, logic synthesis and timing analysis.… more
    NVIDIA (11/20/25)
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  • Senior ASIC Design

    NVIDIA (Santa Clara, CA)
    We are now looking for a motivated Senior ASIC Design Engineer to join our dynamic and growing team in our Circuit Solutions Group! NVIDIA has ... with Verilog/SystemVerilog + Strong familiarity and experience with all stages of ASIC design flow including front end design and verification, DFT, and… more
    NVIDIA (11/26/25)
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  • Senior ASIC Design

    NVIDIA (Santa Clara, CA)
    We are now looking for a Senior ASIC Design Engineer - DFX NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 ... imagination and intelligence. Make the choice to join us today. Design -for-Test Engineering at NVIDIA works on groundbreaking innovations involving crafting creative… more
    NVIDIA (10/25/25)
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  • Senior ASIC Physical Design

    NVIDIA (Santa Clara, CA)
    …human inventiveness and intelligence. We are now looking for a motivated Senior ASIC Physical Design Engineer , Netlisting to join our dynamic and growing ... What you'll be doing: + You will drive physical design of high-frequency and low-power CPUs, GPUs, SoCs at...checks, etc. + Help in all aspects of physical design , such as driving timing convergence, timing constraints generation… more
    NVIDIA (10/22/25)
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  • Senior ASIC Engineer , IP…

    Google (San Diego, CA)
    Senior ASIC Engineer , IP Design , Silicon _corporate_fare_ Google _place_ Mountain View, CA, USA; San Diego, CA, USA **Mid** Experience driving progress, ... or equivalent practical experience. + 8 years of experience with RTL design using Verilog/System Verilog and microarchitecture. + Experience with a scripting… more
    Google (12/06/25)
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  • Senior ASIC Design

    NVIDIA (Santa Clara, CA)
    NVIDIA is seeking best-in-class ASIC Design Engineers to design and implement the world's leading SoC's and GPU's. This position offers the opportunity to ... or Computer Engineering. + 5+ years of proven experience working on ASIC design and development. + Experience in micro-architecture and RTL development of… more
    NVIDIA (12/10/25)
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  • Senior ASIC Design

    NVIDIA (Santa Clara, CA)
    …Make the choice to join us today. The clocks group is looking for a top-notch ASIC engineer to join the team. The Team is responsible for crafting all aspects ... and DFT teams. + Get involved in end-to-end cycle of ASIC execution starting from micro-arch, design implementation, design fixes, sign-off checks and all… more
    NVIDIA (10/28/25)
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  • Senior ASIC Design

    Amazon (San Diego, CA)
    …degree in Electrical Engineering or a related field - 7+ years of digital design in communication systems experience - Experience with products that have gone to ... volume production - Experience in low power design techniques Preferred Qualifications - Master's degree or Ph.D....Engineering or related field - 10+ years in digital design , preferably in communication systems - Familiarity with UVM… more
    Amazon (11/18/25)
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  • Senior ASIC Physical Design

    NVIDIA (Santa Clara, CA)
    design is preferred. + Verilog expertise is preferred as is a deep understanding of ASIC design flow including RTL design and verification, DFT, and ECO. ... As a member of our CPU Cache Coherent Interconnects Design Team, you will be responsible for the physical... Team, you will be responsible for the physical design of CPU on-chip interconnect network and last-level caches,… more
    NVIDIA (11/20/25)
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