- NVIDIA (Santa Clara, CA)
- …efficiency and support + Improve the speed, flexibility and extensibility of the GPU front end build flow + Keep the GPU Continuous Integration system at ... NVIDIA is seeking elite ASIC RTL/Verification ASIC engineers to develop the core Verification and RTL infrastructure of the world's leading GPUs. This position… more
- SpaceX (Irvine, CA)
- Sr. SOC/ ASIC Timing Signoff & Front - End Implementation Engineer (Silicon Engineering) Irvine, CA Apply SpaceX was founded under the belief that a future ... ultimate goal of enabling human life on Mars. SR. SOC/ ASIC TIMING SIGNOFF & FRONT - END ...as needed COMPENSATION & BENEFITS: Pay range: Synthesis and Front - End STA Engineer/ Senior : $160,000.00 -… more
- Cisco (San Jose, CA)
- …DV, DFT, physical design, and post-silicon validation The team comprises micro-architects, front - end designers, and verification engineers. Cisco is a system ... What You'll Do * You will participate in the ASIC design verification for Cisco high- end switching products. * Development of simulation models, test plans,… more
- NVIDIA (Santa Clara, CA)
- …be doing: + Improve the speed, flexibility, and extensibility of the High-Speed IO front end integration, build, and verification flows + Apply best in class ... NVIDIA is seeking outstanding Senior Design Verification Engineers with a specialty in...of relevant industry experience + Exposure to computer architecture, ASIC design, and verification methodology is required + Experience… more
- Qualcomm (San Diego, CA)
- …power, performance, and area of the IPs - Assist in running the full suite of front - end ASIC design tools (lint checking, CDC, DFT, synthesis, FV, STA, etc.) ... Summary:** Qualcomm mixed-signal IP design team is seeking talented senior ASIC digital designers to join our...experience in micro-architecture and RTL design - Proficiency with front - end ASIC design tools such… more
- Cisco (San Jose, CA)
- … senior DFT verification lead in San Jose, CA. You will work with Front - end RTL teams, backend physical design teams to understand chip architecture and drive ... high-quality DFT verification. What You'll Do: * Responsible for thorough test planning and development of test benches to verify comprehensive Design-for-Test (DFT) architecture that supports ATE screening, in-system test, debug and diagnostics needs of the… more
- L3Harris (Anaheim, CA)
- …industry. With customers' mission-critical needs always in mind, our employees deliver end -to- end technology solutions connecting the space, air, land, sea and ... cyber domains in the interest of national security. Job Title: Senior Manager, Engineering Manager Job Code: 22201 Job Location: Location: Anaheim, CA. Job Schedule:… more
- NVIDIA (Santa Clara, CA)
- …diverse team creating NVIDIA's chip design methodology! We're responsible for the Front - End Design Implementation methodology for all of NVIDIA's semiconductor ... design implementation and analysis tools + Provide support for ASIC tools and flows + Assist chip design teams...experience; MS preferred + Be familiar with Verilog and ASIC design along with experience in commercial EDA tools… more
- Cadence Design Systems, Inc. (San Jose, CA)
- …changes and improved / drive timing to closure. + The position will interact with both Front End (Design / DFT) and Back End Implementation Teams (P&R). + ... and passionate engineering team building the next Palladium Emulation ASIC and system at Cadence Design System. Palladium has...computer engineering with a minimum of 10 years of ASIC Design experience OR MS with a minimum of… more
- quadric.io, Inc (Burlingame, CA)
- …Ph.D. in Electrical or Computer Engineering with a minimum of five years of CPU/GPU/ ASIC front - end design + Proficiency in SystemC, SystemVerilog, or Verilog ... floor of a revolutionary new processor architecture. As a senior member of our chip design team, you will...+ Contribute to timing closure through full product cycle ( front end , back- end , tapeout) Requirements:… more
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