- SanDisk (Milpitas, CA)
- …+ Coordinate effectively with SoC Design , SoC Design Verification, ASIC Validation, DFT, Physical Design , Hardware, Mixed Signal IPs, Foundry, ... + Maintain and enforce the highest industry standards and best practices in ASIC design development. Provide mentorship and guidance to team members, fostering… more
- Silvus Technologies (Irvine, CA)
- …+ Experience using MATLAB. + Experience with communication systems on FPGA or ASIC designs. WORKING CONDITIONS & PHYSICAL REQUIREMENTS + Office environment. + ... to a fulfilling career._ THE OPPORTUNITY Silvus is seeking a **_Senior FPGA/RTL Design Engineer_** who will report to the _Director of FPGA Engineering_ on the… more
- SanDisk (Irvine, CA)
- …the Firmware on SoC platforms, as well as bringing up of FPGA and ASIC . + Contribute to the Security Development Lifecycle of the Firmware by supporting its ... development at different stages, including design , threat analysis, implementation, validation, vulnerability testing, certification, and audit. **Qualifications**… more
- Silvus Technologies (Irvine, CA)
- …presentation skills. + Experience with wireless communication systems on FPGA or ASIC designs. WORKING CONDITIONS & PHYSICAL REQUIREMENTS + Office environment. ... career._ THE OPPORTUNITY Silvus is seeking a **_Principal FPGA / RTL Design Engineer- Signal Processing_** who will report to the _Senior Engineering Director_… more
- Google (Sunnyvale, CA)
- Senior ASIC Physical Design Engineer _corporate_fare_ Google _place_ Sunnyvale, CA, USA **Mid** Experience driving progress, solving problems, and ... focus on TPU architecture and its integration within AI/ML-driven systems. As an ASIC Physical Design Engineer, you will collaborate with RTL, Design … more
- NVIDIA (Santa Clara, CA)
- …Cache Coherent Interconnects Design Team, you will be responsible for the physical design of CPU on-chip interconnect network and last-level caches, working ... our CPU team, you'll be a liaison between Logic design and Physical design teams...expertise is preferred as is a deep understanding of ASIC design flow including RTL design… more
- NVIDIA (Santa Clara, CA)
- …timing paths through ECOs including crosstalk and noise analysis. + Expertise in physical design and optimization eg, placement, routing, cell sizing, buffering, ... work, to amplify human inventiveness and intelligence. We are now looking for a motivated ASIC Timing Engineer to join our dynamic and growing team. If you want to… more
- NVIDIA (Santa Clara, CA)
- NVIDIA is looking for a Senior ASIC Design Engineer to join our Memory Subsystem Team! As a Senior ASIC Design engineer at NVIDIA, you'll join a ... Subsystem Design team, you will collaborate with architects/ design verification/formal verification/ physical design team...a plus. + Experience with all stages in the ASIC design flow including emulation, prototyping, DFT,… more
- Cisco (San Jose, CA)
- … ASIC team can provide. You will work with exceptional talent with vast ASIC design and development expertise. With Cisco being a systems company, you will ... **Sr. ASIC Engineer** The application window is expected to...refining design and timing constraints for seamless physical design closure. As part of this… more
- NVIDIA (Santa Clara, CA)
- NVIDIA is looking for a Senior Reset and Boot ASIC Engineer...doing: + Be an integral part of the System ASIC Design team to help with the ... functions like Reset or Chip Boot + Solid frontend ASIC design skills, including RTL design...CHI + Familiar with OCP secure boot specification and physical security handling process + Possess design … more
