- NVIDIA (Santa Clara, CA)
- …join our diverse team today. We are now looking for a highly motivated and talented Senior DFT Infrastructure Engineer to join our DFX group to join this ... tools for ATE test vector release and fail analysis/diagnosis flows + Work with DFT , ATE bringup, Silicon FA teams + Create regression testcases to ensure flow… more
- NVIDIA (Santa Clara, CA)
- …Make the choice to join us today. NVIDIA's DFX team is looking for an exceptional DFT Engineer to help shape the future of compute. As stewards of the entire ... teams to drive scalable, automated solutions. + Co-architect novel DFT strategies alongside VLSI and Product Engineering teams to...field + 5+ years of hands-on experience in Design-For-Test ( DFT ) + Deep knowledge of DFT tools,… more
- NVIDIA (Santa Clara, CA)
- …experience) with 5+, MSEE with 3+, or PhD with 2+ years of experience in DFT , system architecture, or RTL design. + Understanding of fundamental DFT topics, such ... of MBIST and IOBIST fundamentals. + Experience in architecting DFT access mechanisms in 3D stacked and dielet/chiplet based...are growing fast. If you're a creative and autonomous engineer with real passion for technology, we want to… more
- SpaceX (Sunnyvale, CA)
- SR. SOC/ASIC DFT Engineer (Silicon Engineering) Sunnyvale, CA Apply SpaceX was founded under the belief that a future where humanity is out exploring the stars ... goal of enabling human life on Mars. SR. SOC/ASIC DFT ENGINEER (SILICON ENGINEERING) At SpaceX we're...as needed COMPENSATION AND BENEFITS: Pay range: Physical Design Engineer / Senior : $170,000.00 - $230,000.00/per year Your actual… more
- Cisco (San Jose, CA)
- Senior DFx/RTL Engineer Apply (https://jobs.cisco.com/jobs/Login?projectId=1447271) + Location:San Jose, California, US + Area of InterestEngineer - Hardware + ... teams, backend physical design teams to understand chip architecture and drive DFT requirements early in the design cycle. **Key Responsibilities:** + Responsible… more
- NVIDIA (Santa Clara, CA)
- …design tradeoffs and methodology on next generation CMOS technology. We are looking for a Senior ASIC Timing Engineer to join our dynamic and growing team! If ... frequency and power/area/congestions/yield/etc. + Work on all aspects of DFT /Test timing such as timing constraints, timing analysis, timing...to stand out from the crowd: + Experience with DFT timing closure for various modes eg scan shift,… more
- NVIDIA (Santa Clara, CA)
- …design tradeoffs and methodology on next generation CMOS technology. We are looking for a Senior ASIC Synthesis Engineer to join our dynamic and growing team! If ... You'll Be doing: + As a Front-End ASIC Synthesis Engineer , you will own RTL synthesis and gate level...power/area optimization across multiple design blocks + Work with DFT and Verification teams to ensure functional and timing… more
- NVIDIA (Santa Clara, CA)
- We are now looking for a motivated Senior ASIC Design Engineer to join our dynamic and growing team in our Circuit Solutions Group! NVIDIA has continuously ... + Work with front-end teams to overlook correctness of the design (Lint/NA/CDC/Synthesis/ DFT /LEC/STA) + Partner and work with back-end team until chip tape-out. +… more
- General Motors (Mountain View, CA)
- …design and development of our vehicle displays hardware. In this role, the Senior Hardware Design Engineer - Display Development will be responsible for ... (DFM), design for assembly (DFA), and design for testing ( DFT ) + Drive the validation and testing of hardware...(DFM), design for assembly (DFA), and design for testing ( DFT ) + Excellent problem-solving, analytical, and communication skills. +… more
- NVIDIA (Santa Clara, CA)
- We are now looking for a Senior ASIC Engineer in the area of DFX ATPG flows and methodologies. Do you like to think creatively and enjoy solving challenges that ... be doing: + Support the deployment of advanced Design-For-Test ( DFT ) and Automatic Test Pattern Generation (ATPG) solutions +...to stand out from the crowd: + Knowledge of DFT including fault models, ATPG, fault simulation, and diagnosis… more
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