• Senior RTL Analysis…

    NVIDIA (Santa Clara, CA)
    …What you'll be doing: + You will be part of NVIDIA's RTL analysis CAD team, responsible for developing flows, methodology , and application support for Clock ... part of a diverse team creating NVIDIA's chip design methodology ! We're responsible for the RTL CDC...deploy, and support state-of-the-art EDA tools and methodologies for RTL analysis . + Serve as an in-house… more
    NVIDIA (05/16/25)
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  • Senior Timing and Constraints…

    NVIDIA (Santa Clara, CA)
    …to amplify human inventiveness and intelligence. We are seeking an innovative senior timing signoff and constraint methodology engineer to develop pioneering ... develop methodology and flows to validate timing constraints from RTL to netlist via structural, functional and cross-hierarchy constraints checks. We're looking… more
    NVIDIA (05/29/25)
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  • Senior Async and IO Timing…

    NVIDIA (Santa Clara, CA)
    …field (or equivalent experience). + 6+ years of experience in static timing analysis , methodology , or constraint development. + Strong expertise in asynchronous ... human inventiveness and intelligence. We are seeking a highly skilled Timing Methodology Engineer with expertise in asynchronous timing and I/O interface modeling to… more
    NVIDIA (05/22/25)
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  • Senior Design for Debug Architect…

    NVIDIA (Santa Clara, CA)
    …now looking for a Senior Design for Debug (DFD) Architect and Methodology Engineer! NVIDIA is seeking a DFD Architect to implement hardware and software ... tools. + Great understanding of ASIC design flow including RTL design, verification, logic synthesis, timing analysis ...including RTL design, verification, logic synthesis, timing analysis and bringup. + Strong interpersonal skills and an… more
    NVIDIA (06/11/25)
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  • Senior GPU Validation and Emulation…

    Qualcomm (San Diego, CA)
    …Engineering, or related field. **Job Description:** + Synthesize the Verilog RTL and create models and compile them to emulators like Veloce/Palladium/Zebu ... emphasis on design partitioning, synthesis, place and route, timing analysis & run time performance. + Drive debug failures...debug. + Work with tool vendors and push the methodology to improve the area/performance of the synthesized FPGA… more
    Qualcomm (06/04/25)
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  • Senior ASIC Design Engineer

    NVIDIA (Santa Clara, CA)
    …In-silicon measurement, Reset and Boot controllers. + You will be responsible for the RTL design, logic synthesis, and timing analysis of several modules. + ... We are now looking for a Senior ASIC Design Engineer to join our System...design concepts and experience in ASIC design flow including RTL design, verification, logic synthesis and timing analysis… more
    NVIDIA (06/19/25)
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  • Senior Physical Design Engineer

    Microsoft Corporation (Mountain View, CA)
    …(PD) domain. + Facilitate coordination across cross-functional teams, including DFT, RTL /Design/IP, Static Timing Analysis (STA), CAD, Architecture, Power & ... will manage and optimize the Cloud infrastructure. We are looking for a ** Senior Physical Design Engineer** to join the team. **Responsibilities** + Accountable for… more
    Microsoft Corporation (07/16/25)
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  • Senior CPU Architecture and Performance…

    Google (Mountain View, CA)
    …CPU architecture and CPU blocks. + Experience in performance modeling, analysis , correlation, and workload characterization. + Experience with C/C++ and scripting ... hardware experiences, delivering unparalleled performance, efficiency, and integration. As a Senior CPU Architecture and Performance Architect, you will be the key… more
    Google (06/26/25)
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  • Senior SoC Design Engineer

    NVIDIA (Santa Clara, CA)
    …chip leads, and customers on SoC IP design, timing closure, power analysis , methodology alignment, and program execution, ensuring success from pre-silicon ... lasting impact on the world. Join NVIDIA as a Senior SoC Design Engineer developing innovative SoC solutions. What...experience). + 10+ years of relevant work experience in RTL development passionate about CPU, GPU, and HPC architectures.… more
    NVIDIA (07/15/25)
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  • Senior ASIC Synthesis Engineer

    NVIDIA (Santa Clara, CA)
    …Group! Work as part of the advanced technology team to optimize design tradeoffs and methodology on next generation CMOS technology. We are looking for a Senior ... You'll Be doing: + As a Front-End ASIC Synthesis Engineer, you will own RTL synthesis and gate level optimization tasks + Collaboration with physical design to… more
    NVIDIA (07/01/25)
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