- NVIDIA (Santa Clara, CA)
- …What you'll be doing: + You will be part of NVIDIA's RTL analysis CAD team, responsible for developing flows, methodology , and application support for Clock ... part of a diverse team creating NVIDIA's chip design methodology ! We're responsible for the RTL CDC...deploy, and support state-of-the-art EDA tools and methodologies for RTL analysis . + Serve as an in-house… more
- NVIDIA (Santa Clara, CA)
- …now looking for a Senior Design for Debug (DFD) Architect and Methodology Engineer! NVIDIA is seeking a DFD Architect to implement hardware and software ... tools. + Great understanding of ASIC design flow including RTL design, verification, logic synthesis, timing analysis ...including RTL design, verification, logic synthesis, timing analysis and bringup. + Strong interpersonal skills and an… more
- NVIDIA (Santa Clara, CA)
- …In-silicon measurement, Reset and Boot controllers. + You will be responsible for the RTL design, logic synthesis, and timing analysis of several modules. + ... We are now looking for a Senior ASIC Design Engineer to join our System...design concepts and experience in ASIC design flow including RTL design, verification, logic synthesis and timing analysis… more
- Microsoft Corporation (Santa Clara, CA)
- …(DPU) team within the Azure Hardware Systems & Infrastructure group is seeking a Senior Silicon Engineer. You will join our front-end silicon team and be responsible ... cutting-edge, high performance, low power, scalable and programmable DPU silicon. As a Senior Silicon Engineer in the Data Processing Unit team you will be… more
- SpaceX (Irvine, CA)
- …for test modes + Timing closure ownership throughout the entire project cycle ( RTL , synthesis, and physical implementation) + Analysis of clock domain crossing ... teams to drive integration, timing, logical equivalence checking and analysis of various IPs into RTL +...Functional ECOs for complex blocks + Deploy and enhance methodology and flows related to timing constraint generation and… more
- Cisco (San Jose, CA)
- …and power requirements. * Contribute to full chip integration and timing methodology / analysis . * Develop and analyze functional coverage. * Help define, ... evolve, and support our design methodology . * Collaborate with the verification team to address design bugs and close code coverage. * Work closely with the physical… more
- NVIDIA (Santa Clara, CA)
- …and intelligence. Be part of a diverse team creating NVIDIA's chip design methodology ! We're responsible for the Front-End Design Implementation methodology for ... to evaluate the industry's most powerful design implementation and analysis tools + Provide support for ASIC tools and...Learning + Experience in other ASIC methodologies such as RTL Lint, CDC, DFT or STA. + Experience with… more
- Qualcomm (Santa Clara, CA)
- …IPs. Experience in SoC low power micro-architecture, low power design and methodology , Power Intent/Implementation, power estimates, power analysis tools and ... IPs. Experience in SoC low power micro-architecture, low power design and methodology , Power Intent/Implementation, power estimates, power analysis tools and… more
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