- Samsung Semiconductor, Inc. (San Jose, CA)
- Position Title: Senior Staff Engineer , Serdes Layout Design To provide the best candidate experience amidst our high application volumes, each candidate ... our Flexible Work policy What Youll Do As a senior high speed mixed-signal layout/analog layout engineer ,...designers to optimize the performance and power consumption of SERDES analog PHY. Location: Daily onsite presence at our… more
- Samsung Semiconductor (San Jose, CA)
- Senior Staff Engineer , Serdes Layout Design Samsung Semiconductor Location: Daily onsite presence at our San Jose, CA headquarters in alignment with our ... Flexible Work policy. What You'll Do As a senior high‑speed mixed‑signal layout/analog layout engineer , you...to optimize the parasitics, reduce area, and improve high‑speed SERDES /analog performance. Estimate schedule and create a plan to… more
- Conductor (San Jose, CA)
- …in alignment with our Flexible Work policy. What You'll Do As a senior high‑speed mixed‑signal layout/analog engineer , you will work with circuit designers ... reference circuits. You will optimize the performance and power consumption of SERDES analog PHY and determine the chip floorplan. Collaborate with remote circuit… more
- Flux Computing (San Francisco, CA)
- Senior / Staff Analog Design Engineer - High Speed SerDes 4 days ago Be among the first 25 applicants The Role We are seeking an experienced Analog /RF ... IC designer to architect, implement and productise the multi‑lane, multi‑standard SerDes (serialiser / deserialiser) interfaces that move data in and out of the OTPU… more
- Samsung Semiconductor, Inc. (San Jose, CA)
- A leading semiconductor firm in San Jose is seeking a Senior Staff Engineer for Serdes Layout Design. This role requires extensive experience in ... high-speed mixed-signal layout, knowledge of CMOS technologies, and the ability to collaborate effectively with circuit designers. The ideal candidate will have a strong background in layout optimization and will be involved in innovative projects within a… more
- Flux Computing (San Francisco, CA)
- …in San Francisco seeks a Senior / Staff Analog Design Engineer to innovate SerDes interfaces for high-speed data transfer. The role includes designing ... high-speed circuits, mentoring, and collaborating with cross-disciplinary teams. Candidates should have over 7 years of experience in high-speed IC design, along with strong problem-solving skills. Benefits include competitive compensation, stock options, and… more
- Advanced Micro Devices, Inc. (San Jose, CA)
- … senior technical contributor that drives end-to-end delivery of SerDes solution, directly contributing to and coordinating implementation and optimization across ... exciting opportunity to work on the cutting edge of SerDes technology. The Person You are a subject matter...are highly valued. Key Responsibilities As an ASIC Design Engineer , your responsibilities span various aspects of SOC design:… more
- Flux Computing (San Francisco, CA)
- Join to apply for the Senior / Staff Digital Design Engineer role at Flux Computing 1 day ago Be among the first 25 applicants Get AI-powered advice on this ... The Role We are seeking highly skilled and motivated Senior / Staff Digital Design Engineers with a strong...to multi‑GHz clock domains and integrating high‑speed IP (eg, SerDes , HBM/DDR, PCIe, 100 GbE or similar). Expertise with… more
- Microchip (San Jose, CA)
- Senior Technical Staff Engineer -...or RISC IP's, high speed interfaces such as PAM4 SerDes , DDR4/5, etc. is a plus. Experience in leading multiple ... FPGA/SoC projects. Travel Time 0% - 25% Physical Attributes Feeling, Handling, Hearing, Other, Seeing, Supervises Others, Talking, Works Alone, Works Around Others Physical Requirements 10% walking, 10% standing, 80% sitting; 100% in doors; Usual business… more
- Advanced Micro Devices (San Jose, CA)
- …and beyond. Together, we advance your career. THE ROLE: We are looking for a self‑motivated senior design engineer to be part of a leading team to drive and ... of digital designs. Multi‑clock domain designs. Experience/knowledge of high‑speed SerDes /Physical layer is a plus. Logic synthesis, timing closure, logical… more
