- Google (Sunnyvale, CA)
- …Science, a related field, or equivalent practical experience. + 5 years of experience in static timing analysis. + Experience in full chip timing sign-off ... ASICs. + Experience in PrimeTime or Tempus TCL scripting and static timing analysis debug. Preferred qualifications: + Experience writing, reviewing and… more
- NVIDIA (Santa Clara, CA)
- …design tradeoffs and methodology on next generation CMOS technology. We are looking for a Senior ASIC Timing Engineer to join our dynamic and growing team! ... experience in Physical design/ Timing . + Experience in full-chip/sub-chip Static Timing Analysis (STA), timing constraints generation and management, and… more
- NVIDIA (Santa Clara, CA)
- …to amplify human inventiveness and intelligence. We are now looking for a motivated ASIC Timing Engineer to join our dynamic and growing team. If you want to ... in Synthesis and Timing + Hands-on experience in full-chip/sub-chip Static Timing Analysis (STA), timing constraints generation and management, and … more
- NVIDIA (Santa Clara, CA)
- …to amplify human inventiveness and intelligence. We are now looking for a motivated ASIC Timing Engineer to join our dynamic and growing team. If you want to ... experience in Timing and STA + Hands-on experience in full-chip/sub-chip Static Timing Analysis (STA) and timing convergence, timing constraints… more
- NVIDIA (Santa Clara, CA)
- …or related field (or equivalent experience). + 6+ years of experience in static timing analysis, methodology, or constraint development. + Strong expertise in ... human inventiveness and intelligence. We are seeking a highly skilled Timing Methodology Engineer with expertise in asynchronous timing and I/O interface… more
- NVIDIA (Santa Clara, CA)
- …next generation of high-performance IPs for CPU, GPU and SOC designs. + Owning static timing analysis and convergence of high-performance designs. + You will be ... responsible for all aspects of timing including setting up timing constraints, timing analysis and closure, ECO implementation, and timing methodologies.… more
- Microsoft Corporation (Mountain View, CA)
- …domain. + Facilitate coordination across cross-functional teams, including DFT, RTL/Design/IP, Static Timing Analysis (STA), CAD, Architecture, Power & ... optimize the Cloud infrastructure. We are looking for a ** Senior Physical Design Engineer ** to join the...including DFT modes and methodologies, with comprehensive experience in Static Timing Analysis (STA) for complex hierarchical… more
- NVIDIA (Santa Clara, CA)
- …EE background with an in-depth understanding of circuits, simulation, library characterization and static timing analysis? Enjoy working on the cutting edge of ... We are now hiring for a Senior Library Design Engineer ! NVIDIA has...advanced process nodes + Hands-on experience with standard cell timing , power, statistical characterization and modeling. Familiar with advanced… more
- NVIDIA (Santa Clara, CA)
- …distribution, chip assembly and P&R, timing closure. + Craft designs for static timing analysis, power and noise analysis and back-end verification. What we ... We are now looking for a Senior Physical Design Engineer . NVIDIA has...+ Already a validated strong power user of P&R, Timing analysis, Physical Verification and IR Drop Analysis CAD… more
- Cisco (San Jose, CA)
- …working with Verilog or System Verilog programming skills + Experience with simulators/synthesis/ static timing constraints and related tools (eg, VCS, DC, ... Senior ASIC Design Engineer Apply (https://jobs.cisco.com/jobs/Login?projectId=1431806)...participate in reviews. + Implement Verilog RTL to meet timing , performance, and power requirements. + Contribute to full… more