• Senior Timing and Constraints…

    NVIDIA (Santa Clara, CA)
    …work, to amplify human inventiveness and intelligence. We are seeking an innovative senior timing signoff and constraint methodology engineer to develop ... this role, you'll develop methodology and flows to validate timing constraints from RTL to netlist via structural, functional and cross-hierarchy … more
    NVIDIA (05/29/25)
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  • Senior Async and IO Timing…

    NVIDIA (Santa Clara, CA)
    …work, to amplify human inventiveness and intelligence. We are seeking a highly skilled Timing Methodology Engineer with expertise in asynchronous timing and ... You will play a critical role in defining cross-domain timing constraints , validating IO timing ...equivalent experience). + 6+ years of experience in static timing analysis, methodology , or constraint development. +… more
    NVIDIA (05/22/25)
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  • Senior ASIC Timing Engineer

    NVIDIA (Santa Clara, CA)
    … including, timing analysis and closure, timing environment, setting up constraints and defining the timing methodology for the next generation of ... next generation CMOS technology. We are looking for a Senior ASIC Timing Engineer to join our...and power/area/congestions/yield/etc. + Work on all aspects of DFT/Test timing such as timing constraints ,… more
    NVIDIA (06/10/25)
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  • Senior ASIC Physical Design…

    NVIDIA (Santa Clara, CA)
    …driving frontend and backend implementation including synthesis, equivalence checking, floor-planning, timing constraints , timing and power convergence, and ... multiple teams. + Apply knowledge and experience to improve timing convergence flows working with the methodology ... Timing + Hands-on experience in full-chip/sub-chip Static Timing Analysis (STA), timing constraints … more
    NVIDIA (06/30/25)
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  • Senior ASIC Timing Engineer

    NVIDIA (Santa Clara, CA)
    …chip level. + Work with PD, DFX, Clocks, and other teams in coming up with timing closure strategy, creating timing constraints , driving timing and power ... ECO implementation + Apply knowledge and experience to improve timing convergence flows working with the methodology ...in full-chip/sub-chip Static Timing Analysis (STA) and timing convergence, timing constraints generation… more
    NVIDIA (06/17/25)
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  • Senior High-Performance ASIC Timing…

    NVIDIA (Santa Clara, CA)
    …and convergence of high-performance designs. + You will be responsible for all aspects of timing including setting up timing constraints , timing analysis ... timing closure of high-speed designs. + Strong background and experience in timing constraints generation, clocking, process variations and signal integrity +… more
    NVIDIA (06/24/25)
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  • Senior ASIC Design Engineer

    Cisco (San Jose, CA)
    …, performance, and power requirements. + Contribute to full chip integration and timing methodology /analysis. + Develop and analyze functional coverage. + Help ... Senior ASIC Design Engineer Apply (https://jobs.cisco.com/jobs/Login?projectId=1431806) + Location:San...or System Verilog programming skills + Experience with simulators/synthesis/static timing constraints and related tools (eg, VCS,… more
    Cisco (07/11/25)
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  • Sr. SOC Design - STA, Hardware Compute Group

    Amazon (Sunnyvale, CA)
    …STA, Crosstalk Delay and Crosstalk Noise analysis for digital ASIC/SoCs. * Full chip timing constraints development, full chip / Sub-System STA and Signoff for a ... latest generation of Echo devices is looking for a Senior SoC Design-STA Engineer to continue to innovate on...complex, multi-clock, multi-voltage SoC. * Streamlining the timing signoff criterions, timing analysis methodologies and… more
    Amazon (07/09/25)
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  • Sr Principal ASIC Design Engineer (NetSec)

    Palo Alto Networks (Santa Clara, CA)
    …like setup/hold constraints and delay sources + **Mentor** junior and senior staff engineers, providing technical guidance and fostering their growth in ASIC ... the digital logic that powers our next-generation firewall platforms. As a Senior Principal Engineer, you will take end-to-end ownership of complex modules or… more
    Palo Alto Networks (07/11/25)
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  • Physical Design Engineer

    Broadcom (San Jose, CA)
    …please Sign-In before you apply.** **Job Description:** **Broadcom is looking for a senior level ASIC physical design engineer. In this highly visible role, you will ... **Experience in developing and implementing Power-grid and high speed clock constraints and specification.** + **Good understanding of physical design verification … more
    Broadcom (07/11/25)
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