- Qualcomm (San Diego, CA)
- … solutions for the Snapdragon chips powering billions of mobile devices. The position requires Signoff Static Timing Analysis (STA) knowledge, with CAD ... to reduce conservatism in Signoff . Responsibilities will include: Improving the Signoff Timing methodology for diverse Mobile, Compute, AI, IoT Snapdragon… more
- Qualcomm (San Diego, CA)
- …for the Snapdragon chips powering billions of mobile devices. The position requires Signoff Timing and spice simulation experience, with CAD development skills ... of STA features and Timing concepts. 2-6 years of experience in Signoff Timing of SoCs at either top-level or block-level. 2-6 years of experience with… more
- Apple Inc. (Sunnyvale, CA)
- Cellular SoC Static Timing Analysis Engineer Do you have a passion for invention and self-challenge? Do you thrive on pushing the limits of what's considered ... As an STA Engineer, the day-to-day work involves performing static timing analysis across multiple...methodologies and flows. Experience in reducing the number of timing signoff corners by merging different … more
- Cadence Design Systems (San Jose, CA)
- …innovators who want to make an impact on the world of technology. Responsibilities: Perform Static timing analysis , glitch, noise analysis using Tempus ... Signoff tool. Execute and deliver various aspects of Timing analysis flows, ECO flows, CAD tools,...at customer sites. Requirements: 10+ years of experience in Static timing analysis . Ability to… more
- Intel Corporation (Folsom, CA)
- …verification and signoff processes including formal equivalence verification and static timing analysis * Perform reliability verification, static ... route, clock tree synthesis, floorplanning, and power/clock distribution for complex**CPU Cores Conduct static timing analysis , reliability analysis , and… more
- Arm Limited (San Diego, CA)
- … timing signoff modes and constraints and familiarity with Synthesis and Static Timing Analysis . Experience in validating and supporting DFT timing ... to support DFT RTL level insertion, synthesis and scan insertion, place-and-route, and static - timing - analysis and timing closure. Participate in ATE… more
- Apple Inc. (San Diego, CA)
- …Collaborating with other teams such as physical design verification, RC extraction, IR and static timing analysis (STA). Working directly with EDA tool ... high performance and low power implementation flows. Understanding of some of the analysis involved in Physical Design - extraction, timing , noise, physical… more
- Qualcomm (San Diego, CA)
- …ASIC/VLSI design tools and flows Strong programming skills in Python Hands‑on experience with static timing analysis (STA) tools, eg, PrimeTime and Tempus ... of the Global SOC organization and is responsible for STA methodology and signoff , foundry technology enablement and analysis , design automation and internal and… more
- The Boeing Company (El Segundo, CA)
- …with us. Boeing Space, Intelligence & Weapons Systems has an exciting opportunity for a ** Static Timing Analysis (STA) Engineer** to join us as part of ... support more Boeing Platforms. We are seeking an experienced Static Timing Analysis Engineer that...around the world from the early design stages until signoff to help achieve first pass success. You will… more
- SpaceX (Irvine, CA)
- …drive execution + Run, debug, and fix signoff closure issues in static timing analysis (STA), noise, logic equivalency, physical verification, ... (eg synthesis, floorplanning, power/ground grid generation, place and route, timing , noise, physical verification, electromigration, voltage drop, logic equivalency… more
