- Qualcomm (San Diego, CA)
- …for the Snapdragon chips powering billions of mobile devices. The position requires Signoff Timing and spice simulation experience, with CAD development skills ... of STA features and Timing concepts. + 2-6 years of experience in Signoff Timing of SoCs at either top-level or block-level. * 2-6 years of experience with… more
- Qualcomm (Santa Clara, CA)
- …for various modes/corners and low-power multi-voltage domain crossings, and signoff with static timing analysis . + Collaborate closely with RTL design ... Team is looking for skilled engineers to focus on timing constraints development, power analysis , STA, and timing closure for premium-tier chips.… more
- Google (Mountain View, CA)
- …. + Be responsible for delivering System-on-Chip (SoC) Static Timing Analysis . + Define SoC timing signoff process corners, derates, uncertainties ... + Experience with ASIC design flows and methodology of static timing analysis . + Experience...full chip timing constraint creation and validation, timing signoff checklist criteria, perform full chip… more
- SpaceX (Sunnyvale, CA)
- …drive execution + Run, debug, and fix signoff closure issues in static timing analysis (STA), noise, logic equivalency, physical verification, ... (eg synthesis, floorplanning, power/ground grid generation, place and route, timing , noise, physical verification, electromigration, voltage drop, logic equivalency… more
- Meta (Sunnyvale, CA)
- …our Infrastructure organization. **Required Skills:** ASIC Implementation Engineer - Static Verification Responsibilities: 1. Perform Flat and Hierarchical Clock ... work with the Designers to create waivers 4. Perform RTL Design for Testability Analysis and improve the Design for Testability coverage for Stuck-at faults 5. Run… more
- Meta (Sunnyvale, CA)
- …equivalent practical experience 10. 12+ years of experience in: STA ( Static Timing Analysis ), Modeling, Signoff methodology development and flows, and ... Area (PPA), and design integrity for Meta SOCs. 2. Develop timing signoff flow/methodology, automation for large complex disaggregated ASICs and test structures… more
- NVIDIA (Santa Clara, CA)
- …Engineering or related field (or equivalent experience). + 6+ years of experience in static timing analysis , methodology, or constraint development. + Strong ... and I/O interface modeling to architect and deploy robust timing signoff practices across high-performance SoCs. You... analysis . + Own and evolve I/O interface timing signoff , including external interface modeling (eg,… more
- Cadence Design Systems, Inc. (San Jose, CA)
- …to success + Strong knowledge in Digital Design Fundamentals, Semiconductor fundamentals, and Static Timing Analysis is required + Prior experience with ... and Signoff including Place and Route, Design Closure, and timing /power signoff + Guide customers on how to best utilize Cadence technologies to… more
- Cadence Design Systems, Inc. (San Jose, CA)
- …related field + Strong knowledge in Digital Design Fundamentals, Semiconductor fundamentals, and Static Timing Analysis is required + Prior experience with ... and Signoff including Place and Route, Design Closure, and timing /power signoff + Guide customers on how to best utilize Cadence technologies to… more
- Qualcomm (San Diego, CA)
- …in die-level IR drop, STA, and power. The engineer should be proficient in static timing analysis using the Synopsys Primetime toolset and should ... analysis ⦁ Develop strategies for 3DIC PDN analysis and signoff **Required Skills and Experience... **Required Skills and Experience :** ⦁ Expertise in static timing analysis . Hands-on… more
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