• Principal IC Static Timing Analysis AE

    Cadence Design Systems, Inc. (San Jose, CA)
    …Route, Clock Tree, RC Extraction and UPF/CPF concepts. . Execute and lead Tempus timing signoff campaigns at existing and new customers. . Automation of flows ... technology. In this senior role you will; Perform Static timing analysis, glitch, noise analysis using Tempus Signoff... tool. Executing and delivering on various aspects of Timing analysis flows, ECO flows, CAD tools… more
    Cadence Design Systems, Inc. (11/13/25)
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  • ASIC Digital Design Engineer

    Teledyne (Goleta, CA)
    …process flow from high-level design to synthesis, place and route, and timing and power use. Analyzes equipment to establish operation data, conducts experimental ... and documentation of customer requirements + Perform digital design, timing design, and detailed digital simulations + Develop IC...closure across PVT corners. + DRC, LVS, extraction and signoff . + Perform RTL Verification & Simulation as needed… more
    Teledyne (11/21/25)
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