- SpaceX (Sunnyvale, CA)
- Sr. SOC /ASIC Physical Design Engineer (Silicon Engineering) Sunnyvale, CA Apply SpaceX was founded under the belief that a future where humanity is out ... possible, with the ultimate goal of enabling human life on Mars. SR. SOC /ASIC PHYSICAL DESIGN ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging… more
- Google (Mountain View, CA)
- …or a related field, or equivalent practical experience. + 4 years of experience in Physical Design . + Experience in one or more synthesis/PnR tools (eg, Genus, ... + Experience with ASIC design flows and methodology of Physical design . + Experience in low power design Implementation including UPF/CPF,… more
- Qualcomm (San Diego, CA)
- …The candidate will work with frontend RTL, DFT, Synthesis, Design Verification and Physical Design teams during the SoC development. Also the candidate ... smarter, connected future for all. As a Qualcomm ASIC Engineer , you will define, model, design (digital...**Responsibilities/Duties:** + Work with frontend RTL, DFT, Synthesis, and Physical design teams in the development of… more
- Google (Sunnyvale, CA)
- …generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. As a SoC Design Engineer , you will join a team working ... on SoC -level RTL design for our data center accelerators. You will ...and debug design RTL. + Work with physical design teams to ensure design...design RTL. + Work with physical design teams to ensure design meets … more
- SpaceX (Irvine, CA)
- …weekends to meet critical deadlines, as needed COMPENSATION & BENEFITS: Pay range: Physical Design STA/Timing Engineer /Level I: $120,000.00 - $145,000.00/per ... SOC /ASIC Timing Signoff & Front-End Implementation Engineer ...year Physical Design STA/Timing Engineer /Level II: $140,000.00 - $170,000.00/per year… more
- SpaceX (Irvine, CA)
- …generation and verification and timing closure + Work closely with chip architecture, design verification, physical design , DFT, and power teams to ... Sr. SOC /ASIC Timing Signoff & Front-End Implementation Engineer...+ Experience with test modes, mode merging to optimize physical design implementation and STA Signoff. +… more
- Datavant (Sacramento, CA)
- …We're Looking For** Become a vital defender of our digital landscape as a SOC /SIRT engineer . You'll monitor and analyze security alerts, swiftly respond to ... effective coordination and communication across technical teams and stakeholders. + Design , mature, and implement advanced playbooks for triage, investigation, and… more
- Meta (Sunnyvale, CA)
- …on Chip ( SoC ) and IP for data center applications. **Required Skills:** ASIC Engineer , Physical Design Responsibilities: 1. Develop and own physical ... Knowledge of geometry/process/device technology implications on physical design . 16. Experience with large SOC designs...physical design . 16. Experience with large SOC designs (>20M gates) with frequencies over 1GHZ. 17.… more
- Qualcomm (Santa Clara, CA)
- … engineering positions in our SOC and core design team. As a physical design engineer you will innovate, develop, and implement chips and cores using ... technologies. You will be part of a team responsible for the complete Physical Design Flow and deliveries of complex, high-speed, low power designs such as GPU,… more
- SpaceX (Irvine, CA)
- Sr. ASIC Design Engineer (Silicon Engineering) Irvine, CA Apply SpaceX was founded under the belief that a future where humanity is out exploring the stars is ... goal of enabling human life on Mars. SR. ASIC DESIGN ENGINEER (SILICON ENGINEERING) At SpaceX we're...digital ASICs and/or FPGAs for Starlink projects, implementing complex SoC blocks and SoC integration tasks +… more