• Sr . IC Layout

    SpaceX (Irvine, CA)
    Sr . IC Layout Designer (Silicon Engineering) Irvine, CA...will be an integral part of the IC design team and lead the discipline of layout at ... the ultimate goal of enabling human life on Mars. SR . IC LAYOUT DESIGNER...to meet critical milestones COMPENSATION AND BENEFITS: Pay range: Layout Designer / Senior : $130,000.00 - $180,000.00/per… more
    SpaceX (06/18/25)
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  • Sr . Manager, Analog Mixed Signal IC

    Teledyne (Camarillo, CA)
    …to the next level with us** ! Teledyne Imaging Sensors is looking for a ** Senior Analog Mixed Signal IC Design engineer** responsible for supporting the ... for a high-functioning team of Digital and Analog mixed-signal IC design engineers. + Collaborate with stakeholders... design including performing full custom analog IC layout . + Thorough understanding of deep… more
    Teledyne (04/29/25)
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  • Sr . Staff IC CAD Engineer

    Power Integrations (San Jose, CA)
    …market transformation. Duties and Responsibilities + Develops and maintains PDKs. + Supports all IC design CAD tools such as Cadence schematic entry, mixed mode ... circuit simulation, layout design , layout verification, logic...management, user support and vendor interface. + Works with IC layout designers providing support for taping… more
    Power Integrations (07/16/25)
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  • Senior Package Layout Engineer…

    NVIDIA (Santa Clara, CA)
    design teams in the design and development of sophisticated, detailed layout of IC substrates for NVIDIA products. In addition, work with design ... To this purpose, we are now seeking a hard-working Senior Package Layout Engineer who is committed...using Cadence APD or SiP tool suite. + Propose layout design trade-offs to the Technical Package… more
    NVIDIA (07/10/25)
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  • Senior Failure Analysis Engineer

    Power Integrations (San Jose, CA)
    IC ATE test data log is required. Ability to interpret system level schematics, the IC level schematics, and IC layout of CMOS and bipolar devices is ... issues. Responsibilities: + Performing fault isolation and defect analysis/characterization on power IC 's to identify root causes of product failures in power supply… more
    Power Integrations (04/22/25)
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  • Sr . Principal Analog IC

    Cadence Design Systems, Inc. (San Jose, CA)
    …to make an impact on the world of technology. The Principal Analog IC Designer is responsible for the design and development of analog/mixed signal IC ... years of experience in CMOS SerDes or high-speed I/O IC design and development + Working knowledge...requires proficiency in using CAD tools for circuit simulation, layout , and physical verification + Cadence tool experience, lab… more
    Cadence Design Systems, Inc. (07/04/25)
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  • Foundry RF IC Technology Development…

    Broadcom (San Jose, CA)
    …Experience with device model development and validation, PDK integration + Experience layout design rule development and validation, PDK integration + Experience ... have a Candidate Account, please Sign-In before you apply.** **Job Description:** Senior RF IC technology pathfinder and applications support engineer supporting… more
    Broadcom (07/12/25)
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  • RF/Analog IC Design Engineer

    Qualcomm (Santa Clara, CA)
    …Qualcomm Atheros, Inc. **Job Area:** Engineering Group, Engineering Group > RFIC Design **General Summary:** Define, design and develop complex radio frequency ... signal path and circuit topology analysis and detailed transistor-level design of highly-integrated transceivers and associated blocks for wireless applications,… more
    Qualcomm (05/29/25)
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  • Sr . Application Support Engineer - Calibre

    Siemens (Fremont, CA)
    …required. + Minimum 3 years experience with Calibre solutions required. Calibre nmDRC ( Design Rule Checking), Calibre nmLVS ( Layout vs. Schematic) and ERC ... Calibre PERC (Programmable Electrical Rule Checking). + Understanding of commercial IC physical design flows + Ability to work in a dynamic environment learning… more
    Siemens (06/22/25)
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  • Heterogeneous Integration Engineer, Sr

    Qualcomm (San Diego, CA)
    …metallization + Product development experience with TSMC SoIC and/or CoWoS + Experience with 2.5D/3D IC design flow and PDK development + System PDN design ... for all. As a Qualcomm ASIC Engineer, you will define, model, design (digital and/or analog), optimize, verify, validate, implement, and document IP (block/SoC)… more
    Qualcomm (06/06/25)
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