• Sr . SOC / ASIC Timing

    SpaceX (Irvine, CA)
    Sr . SOC / ASIC Timing Signoff & Front-End Implementation Engineer (Silicon Engineering) Irvine, CA Apply SpaceX was founded under the belief that a future ... the ultimate goal of enabling human life on Mars. SR . SOC / ASIC TIMING ...COMPENSATION & BENEFITS: Pay range: Synthesis and Front-End STA Engineer/ Senior : $160,000.00 - $220,000.00/per year Your actual level and… more
    SpaceX (04/15/25)
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  • Sr . SOC / ASIC Physical…

    SpaceX (Sunnyvale, CA)
    Sr . SOC / ASIC Physical Design Engineer (Silicon Engineering) Sunnyvale, CA Apply SpaceX was founded under the belief that a future where humanity is out ... to make this possible, with the ultimate goal of enabling human life on Mars. SR . SOC / ASIC PHYSICAL DESIGN ENGINEER (SILICON ENGINEERING) At SpaceX we're… more
    SpaceX (04/15/25)
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  • Sr . ASIC Design Engineer (Silicon…

    SpaceX (Irvine, CA)
    Sr . ASIC Design Engineer (Silicon Engineering) Irvine,... clean design + Participate in all phases of ASIC and/or FPGA design flow (eg synthesis, timing ... the ultimate goal of enabling human life on Mars. SR . ASIC DESIGN ENGINEER (SILICON ENGINEERING) At...problems including clock domain crossings and power optimization + ASIC / SoC system integration experience + Experience with… more
    SpaceX (04/15/25)
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  • Senior High-Performance ASIC

    NVIDIA (Santa Clara, CA)
    …plans for NVIDIA's next generation of high-performance IPs for CPU, GPU and SOC designs. + Owning static timing analysis and convergence of high-performance ... experience or MS (or equivalent experience) with 3+ years' experience in ASIC Design and Timing + Hands-on experience in STA tools, ECO implementation, and … more
    NVIDIA (03/25/25)
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  • Sr . ASIC Design Engineer, Project…

    Amazon (San Diego, CA)
    …role you will: . Work closely with the system architects to develop world-class SOC and IP blocks, which meet power, area and performance targets. . Define, ... configure and integration SoC Subsystems . Contribute to the SoC ...DFT on the blocks . Perform initial synthesis & timing analysis . Assist verification team in unit verification… more
    Amazon (02/15/25)
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  • Senior ASIC Design Engineer

    NVIDIA (Santa Clara, CA)
    We are now looking for a Senior ASIC Design Engineer to join our System ASIC team! NVIDIA has continuously reinvented itself over two decades. Our invention ... to design and implement the world's leading GPU and SoC 's. With the System- ASIC team, you will...be responsible for the RTL design, logic synthesis, and timing analysis of several modules. + Integrate modules into… more
    NVIDIA (03/20/25)
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  • Senior ASIC Design Engineer

    Tarana Wireless (Milpitas, CA)
    This position will challenge you! The Senior ASIC Engineer will work on complex ASIC designs for our point to multipoint wireless products. + Architecture ... circuits using Verilog + Frontend design development and integration of large ASIC designs including: Integration of Processors, Bus, Memory, and Interface IPs +… more
    Tarana Wireless (05/01/25)
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  • Senior ASIC Design Engineer

    NVIDIA (Santa Clara, CA)
    We are now looking for a Senior ASIC Design Engineer. NVIDIA is seeking ASIC Design Engineers to implement the world's leading SoC 's and GPU's. This ... Craft micro-architecture, implement in RTL, and deliver a fully verified, synthesis/ timing clean design. + Collaborate and coordinate with architects, other… more
    NVIDIA (03/12/25)
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  • Senior ASIC Design Engineer

    NVIDIA (Santa Clara, CA)
    NVIDIA is seeking an outstanding Senior ASIC Design Engineer to design and implement the world's leading SoC 's and GPU's. This position offers the ... fully verified design by working closely with verification engineers. + Deliver a synthesis/ timing clean design while working with the physical design team to ensure… more
    NVIDIA (05/02/25)
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  • ASIC Design Engineer, Cloud-Scale Machine…

    Amazon (Cupertino, CA)
    …scale and rapid integration of emergent technologies. We're looking for an ASIC Design Eengineer to help us trail-blaze new technologies and architectures, while ... job responsibilities - integrate multiple subsystems into top level SOC , ensure correct clock/reset/functional/DFT signal routing - As a...signal routing - As a key member of the ASIC design team, you will implement and deliver high… more
    Amazon (04/23/25)
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