• Static Timing Analysis

    The Boeing Company (El Segundo, CA)
    …future with us. Boeing Space, Intelligence & Weapons Systems has an exciting opportunity for a ** Static Timing Analysis ( STA ) Engineer** to join us as ... Missiles & Weapons; Strike, Surveillance and Mobility; and Autonomous Systems). As a Static Timing Analysis ( STA ) Engineer you will handle pre-layout and… more
    The Boeing Company (01/09/26)
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  • Senior ASIC Timing Engineer

    NVIDIA (Santa Clara, CA)
    …2 years experience in Timing and STA + Hands-on experience in full-chip/sub-chip Static Timing Analysis ( STA ) and timing convergence, ... inventiveness and intelligence. What you'll be doing: + Drive timing analysis and closure of Nvidia's GPUs,.... + Expertise and in-depth knowledge of industry standard STA and timing convergence tools. + Knowledge… more
    NVIDIA (12/10/25)
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  • Senior ASIC Physical Design and Timing

    NVIDIA (Santa Clara, CA)
    …2+ years experience in Synthesis and Timing + Hands-on experience in full-chip/sub-chip Static Timing Analysis ( STA ), timing constraints ... inventiveness and intelligence. What you'll be doing: + Drive timing analysis and closure of Nvidia's GPUs,...out from the crowd: + Background in domain specific STA and timing convergence, such as CPUs,… more
    NVIDIA (11/22/25)
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  • ASIC Physical Design and Timing Engineer

    NVIDIA (Santa Clara, CA)
    …MS (preferred) in Electrical or Computer Engineering with 2 years' experience + Experience with Static Timing Analysis ( STA ) + Experience physical design ... inventiveness and intelligence. What you'll be doing: + Drive Physical Design and timing analysis and closure of NVIDIA's GPUs, CPUs, DPUs and SoCs at block… more
    NVIDIA (10/17/25)
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  • Lead Application Engineer

    Cadence Design Systems, Inc. (San Jose, CA)
    …tools for Synthesis, Logical Equivalency Checking (LEC), Design-for-Test (DFT), Place & Route and Static Timing Analysis ( STA ).You may get involved in ... Or Cadence or Synopsys place and route tools (Physical Synthesis, PnR, CTS, Static Timing Analysis ) + Debug and resolve complicated PPA, Low Power… more
    Cadence Design Systems, Inc. (12/03/25)
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  • Sr. SOC/ASIC Physical Design Engineer (Silicon…

    SpaceX (Sunnyvale, CA)
    …potential solutions and drive execution + Run, debug, and fix signoff closure issues in static timing analysis ( STA ), noise, logic equivalency, physical ... (eg synthesis, floorplanning, power/ground grid generation, place and route, timing , noise, physical verification, electromigration, voltage drop, logic equivalency… more
    SpaceX (01/07/26)
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  • Senior ASIC Physical Design Engineer

    Google (Sunnyvale, CA)
    …+ Experience working with external partners on Physical Design (PD) closure. + Experience in Static Timing Analysis ( STA ), with an understanding of how ... to GDSII, including key stages like floorplanning, place and route, and timing closure). + Experience in Python, Tcl, or Perl scripting. **Preferred… more
    Google (12/18/25)
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  • Physical Design Engineer, University Graduate, PhD

    Google (Sunnyvale, CA)
    …device physics and transistor structures (eg, finfet, Gate all around). + Understanding of Static Timing Analysis ( STA ), Clock Domain Crossings (CDC), ... as Verilog, facilitating effective collaboration with logic design teams to resolve timing issues. + Knowledge of fundamental VLSI and physical design principles,… more
    Google (12/24/25)
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  • Senior Silicon Bringup and Test Lead, Raxium

    Google (Fremont, CA)
    …Design for Testability (DFT) implementation. + Experience with industry-standard EDA tools for synthesis, Static Timing Analysis ( STA ), and DFT. + ... relevant Electronic Design Automation (EDA) tools for circuit design and analysis . **Preferred qualifications:** + 15 years of experience in Application-Specific… more
    Google (01/07/26)
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  • Principal IC Static Timing

    Cadence Design Systems, Inc. (San Jose, CA)
    …make an impact on the world of technology. In this senior role you will; Perform Static timing analysis , glitch, noise analysis using Tempus Signoff ... Work on SDC constraints, advanced OCV/SOCV concepts, derates, PBA timing , Distributed and Concurrent STA flows. ....and customer sites. Requirements; 8+ years of experience in Static timing analysis , Individual should… more
    Cadence Design Systems, Inc. (11/13/25)
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