- Google (Mountain View, CA)
- …technology process nodes. + Experience with ASIC design flows and methodology of static timing analysis . + Experience in extraction of design ... Google (https://careers.google.com/benefits/) . + Be responsible for delivering System-on-Chip (SoC) Static Timing Analysis . + Define SoC timing signoff… more
- Qualcomm (San Diego, CA)
- …Snapdragon chips powering billions of mobile devices. The position requires Signoff Timing and spice simulation experience, with CAD development skills to define and ... for accuracy, compute, in close collaboration with Snapdragon Physical Design and Timing teams. Qualcomm is using leading edge internal and EDA technologies in… more
- Google (Sunnyvale, CA)
- … (ie, full chip timing signoff ownership, constraint authoring and verification, full chip static timing analysis and timing ECO creation, timing ... crosstalk. Preferred qualifications: + 10 years of experience in the domain of static timing analysis . + Experience leading one or more aspects of physical… more
- Google (Sunnyvale, CA)
- … (eg, full chip timing signoff ownership, constraint authoring and verification, full chip static timing analysis and timing ECO creation, timing ... crosstalk). Preferred qualifications: + 7 years of experience in the domain of static timing analysis . + Experience leading one or more aspects of physical… more
- Meta (Sunnyvale, CA)
- …Engineers within our Infrastructure organization. **Required Skills:** ASIC Implementation Engineer - Static Verification Responsibilities: 1. Perform Flat ... work with the Designers to create waivers 4. Perform RTL Design for Testability Analysis and improve the Design for Testability coverage for Stuck-at faults 5. Run… more
- NVIDIA (Santa Clara, CA)
- …with 2 years experience in Timing and STA + Hands-on experience in full-chip/sub-chip Static Timing Analysis (STA) and timing convergence, timing ... intelligence. We are now looking for a motivated ASIC Timing Engineer to join our dynamic and...inventiveness and intelligence. What you'll be doing: + Drive timing analysis and closure of Nvidia's GPUs,… more
- NVIDIA (Santa Clara, CA)
- …years experience in Synthesis and Timing + Hands-on experience in full-chip/sub-chip Static Timing Analysis (STA), timing constraints generation and ... intelligence. We are now looking for a motivated ASIC Timing Engineer to join our dynamic and...inventiveness and intelligence. What you'll be doing: + Drive timing analysis and closure of Nvidia's GPUs,… more
- NVIDIA (Santa Clara, CA)
- …+ 8+ years experience in Physical design/ Timing . + Experience in full-chip/sub-chip Static Timing Analysis (STA), timing constraints generation and ... CMOS technology. We are looking for a Senior ASIC Timing Engineer to join our dynamic and...+ You will be responsible for all aspects of timing including, timing analysis and… more
- Cisco (San Jose, CA)
- ASIC Design Engineer - Design & Timing Constraints...development in functional and test modes + Experience in Static Timing Analysis and prior ... of our systems, leveraging the latest technology. We're seeking a talented ASIC engineer with a proven track record in high-performance products, ready to make a… more
- NVIDIA (Santa Clara, CA)
- …Engineering or related field (or equivalent experience). + 6+ years of experience in static timing analysis , methodology, or constraint development. + Strong ... work, to amplify human inventiveness and intelligence. We are seeking a highly skilled Timing Methodology Engineer with expertise in asynchronous timing and… more
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