- Google (San Diego, CA)
- …technology process nodes. + Experience with ASIC design flows and methodology of static timing analysis . + Effective skills with scripting languages ... Google (https://careers.google.com/benefits/) . + Be responsible for delivering System-on-Chip (SoC) Static Timing Analysis . + Define SoC timing signoff… more
- Qualcomm (San Diego, CA)
- …Snapdragon chips powering billions of mobile devices. The position requires Signoff Timing and spice simulation experience, with CAD development skills to define and ... for accuracy, compute, in close collaboration with Snapdragon Physical Design and Timing teams. Qualcomm is using leading edge internal and EDA technologies in… more
- Google (Sunnyvale, CA)
- … (ie, full chip timing signoff ownership, constraint authoring and verification, full chip static timing analysis and timing ECO creation, timing ... crosstalk. Preferred qualifications: + 10 years of experience in the domain of static timing analysis . + Experience leading one or more aspects of physical… more
- Meta (Sunnyvale, CA)
- …experience in front-end implementation from RTL to netlist, including RTL Lint, CDC analysis , timing constraints, synthesis to build efficient System on Chip ... (SoC) and IP for data center applications. **Required Skills:** ASIC Implementation Engineer - Static Verification Responsibilities: 1. Perform Flat and… more
- SpaceX (Irvine, CA)
- …Bachelor's degree in electrical engineering, computer engineering or computer science + Experience in static timing analysis and/or timing closure of ... critical deadlines, as needed COMPENSATION & BENEFITS: Pay range: Physical Design STA/ Timing Engineer /Level I: $120,000.00 - $145,000.00/per year Physical Design… more
- Meta (Sunnyvale, CA)
- … timing analysis , SI noise analysis 13. Experience with running Static Timing Analysis for full chip using DMSA 14. Knowledge of front-end and ... experience in front-end implementation from RTL to netlist, including RTL Lint, CDC analysis , timing constraints, synthesis to build efficient System on Chip… more
- NVIDIA (Santa Clara, CA)
- …with 2 years experience in Timing and STA + Hands-on experience in full-chip/sub-chip Static Timing Analysis (STA) and timing convergence, timing ... intelligence. We are now looking for a motivated ASIC Timing Engineer to join our dynamic and...inventiveness and intelligence. What you'll be doing: + Drive timing analysis and closure of Nvidia's GPUs,… more
- Cisco (San Jose, CA)
- …with block/full chip SDC development in functional and test modes. * Experience in Static Timing Analysis and prior working experience with STA tools ... of our systems, leveraging the latest technology. We're seeking a talented ASIC engineer with a proven track record in high-performance products, ready to make a… more
- NVIDIA (Santa Clara, CA)
- …next generation of high-performance IPs for CPU, GPU and SOC designs. + Owning static timing analysis and convergence of high-performance designs. + You ... be responsible for all aspects of timing including setting up timing constraints, timing analysis and closure, ECO implementation, and timing … more
- Qualcomm (Santa Clara, CA)
- …setup for various modes/corners and low-power multi-voltage domain crossings, and signoff with static timing analysis . + Collaborate closely with RTL design ... Team is looking for skilled engineers to focus on timing constraints development, power analysis , STA, and timing closure for premium-tier chips.… more