• System Verilog UVM…

    US Tech Solutions (Goleta, CA)
    …AXI, JTAG preferred + Experience in analog and real number modeling preferred **Skills:** + UVM / System Verilog + Design Verification + Ethernet, SPI, ... **Hybrid** **Job Description:** + The project relates to the design and verification of a custom controller for analog...simulations + Experience in ethernet and SPI required + UVM / System Verilog experience 5+ years… more
    US Tech Solutions (05/08/25)
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  • Senior ASIC Design Verification Engineer

    Cisco (San Jose, CA)
    …combined with 5 years of related experience * Experience in System Verilog / UVM . * Experience with ASIC design and verification processes, debugging, ... with outstanding talent and vast ASIC development expertise in design , DV, DFT, physical design , and post-silicon...micro-architects, front-end designers, and verification engineers. Cisco is a system company, so you can also use the ASIC… more
    Cisco (03/05/25)
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  • Senior E/E & Semiconductor Engineer - Mixed-Signal…

    Capgemini (San Jose, CA)
    …composite models maintained by other groups. **Required Skills** + AMS Verification, UVM / System Verilog , Python, Synopsys/Cadence EDA Verifications Tools. + ... will be involved in development of Analog/Mixed-Signal model in System - Verilog , development of UVM Testbench...design for mixed signal control loops and designing Verilog / Verilog - A code to control… more
    Capgemini (03/19/25)
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  • Senior Design Verification Engineer, HW…

    Amazon (Sunnyvale, CA)
    …10+ years or more of practical semiconductor design verification experience including System Verilog , UVM , assertions and coverage driven verification. - ... test plans for verification of the full chip or sub- system by working with design engineers and...CPU, NPU, and SOC. - Drive Verification Methodology using System Verilog / C++ based test benches.… more
    Amazon (04/16/25)
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  • GPU Design Verification Engineer, Staff

    Qualcomm (San Diego, CA)
    …and tools. + Creates and maintains verification test benches and environments in System Verilog / UVM + Create and leverage advanced testing frameworks ... experience + Verification skills: Test planning, Scripting, Simulation, problem solving and debug. + System Verilog , UVM , Verilog or VHDL, C/C++ skills… more
    Qualcomm (04/16/25)
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  • Senior E/E & Semiconductor Engineer…

    Capgemini (San Francisco, CA)
    …+ Extract modeling specifications from designers + Development of Analog/Mixed-Signal model in System - Verilog + Development of UVM Testbench and developing ... by other groups **Required Skills:** + Good knowledge of System - Verilog RTL coding including state machines, adders,...design for mixed signal control loops and designing Verilog / Verilog - A code to control… more
    Capgemini (03/18/25)
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  • ASIC Design Verification Engineer

    Broadcom (Irvine, CA)
    …evolve rapidly at every generation in a very dynamic market using industry proven methodologies using System Verilog and UVM . You can become a member of an ... of a stable team developing silicon products for Ethernet systems in the Cloud? Come join this team creating... UVM , well versed in OOP_** **_T_** **_ools/Languages: System Verilog (TB structures - Class, SVA,… more
    Broadcom (04/29/25)
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  • Verification Engineer

    Actalent (Sunnyvale, CA)
    …This role requires hands-on experience with verification methodologies and languages such as UVM and System Verilog . Responsibilities + Define electrical ... verification methodologies for various systems by collaborating with researchers, architects, and ...infrastructure. + Create and enhance constrained-random verification environments using System Verilog and UVM , ensuring… more
    Actalent (05/01/25)
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  • Design Verification Engineer (eInfochips…

    Arrow Electronics (Sunnyvale, CA)
    …**Job Description:** **What candidate will Be Doing:** + At-least 8+ years of experience in System Verilog HVL and C++/C + At-least 8+ year of experience in ... **Position:** Design Verification Engineer (eInfochips Inc) **Job Description:** **Role:...Looking For:** + At-least 8+ years of experience in System Verilog HVL and C++/C + At-least… more
    Arrow Electronics (03/12/25)
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  • Asic Manager, Design Verification

    Meta (Sunnyvale, CA)
    …Requires 5 years of experience in the following: 10. 1. Experience in HDL language ( System Verilog , or Verilog ), and scripting language (TCL, Python, Perl, ... (or foreign degree equivalent) in Computer Science, Engineering, Information Systems , Analytics, Mathematics, Physics, Applied Sciences, or a related...or Shell-scripting) 11. 2. Design Verification in Verification methodologies ( UVM or… more
    Meta (03/27/25)
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