- US Tech Solutions (Goleta, CA)
- …and AXI to driven the internal components and send data. **Responsibilities** + As a UVM / SystemVerilog Design Verification Engineer, you will own ... **Job Description:** + The project relates to the design and verification of a custom...with verification methodologies and languages such as UVM and SystemVerilog . + Experience developing and… more
- Meta (Sunnyvale, CA)
- … verification 9. 6+ years of experience in IP/sub-system and/or SoC level verification based on SystemVerilog UVM /OVM based methodologies 10. Experience ... responsible for the verification closure of a design module or sub-system from test-planning, UVM based test bench development to verification closure.… more
- Meta (Sunnyvale, CA)
- … verification 10. 8+ years experience in IP/sub-system and/or SoC level verification based on SystemVerilog UVM /OVM based methodologies 11. Experience ... responsible for the verification closure of a design module or sub-system from test-planning, UVM based test bench development to verification closure.… more
- Meta (Sunnyvale, CA)
- … verification 10. 8+ years of experience in IP/sub-system and/or SoC level verification based on SystemVerilog UVM /OVM based methodologies 11. Experience ... at the entire stack, through algorithms to architecture, transistors to firmware.As a Design Verification Engineer at Meta's Reality Labs, you will work with… more
- Meta (Sunnyvale, CA)
- … UVM methodology 10. 2+ years experience in IP/sub-system and/or SoC level verification based on SystemVerilog UVM /OVM based methodologies 11. Experience ... transistor, through architecture, to firmware, and algorithms. As a Design Verification Engineer at Meta Reality Labs,...14. Experience in development of UVM based verification environments from scratch 15. Experience with Design… more
- Qualcomm (Santa Clara, CA)
- …planning for digital power IP's, its testbench development using the advanced verification methodology such as SystemVerilog - UVM , coverage development, ... related field + 10+ years of experience with ASIC design and verification tools, techniques, and methodology...and methodology + 12+ years of experience with digital design concepts and RTL languages such as SystemVerilog… more
- Northrop Grumman (Mcclellan, CA)
- …SystemVerilog ). Experience with SystemVerilog Assertions (SVA) and Universal Verification Methodology ( UVM ) is required. Successful candidates will have ... + Experience with SystemVerilog Assertions (SVA) + Knowledge of Universal Verification Methodology ( UVM ) + Experience with scripting languages (Bash, Perl,… more
- Amazon (Sunnyvale, CA)
- …working with design engineers and architects - Create and enhance constrained-random verification environments using SystemVerilog and UVM and write SVA. ... What will you help us create? As a Sr. Design Verification Engineer at Amazon, you will...CS. - 7+ years of hands-on experience in Verilog, SystemVerilog , C/C++ based verification and UVM… more
- Google (Sunnyvale, CA)
- …logic at RTL using SystemVerilog for ASICs. + Experience in memory subsystem design verification . + Experience in Power aware verification , Gate level ... engineers to identify important verification scenarios. + Create a constrained-random verification environment using SystemVerilog and UVM . + Identify… more
- Meta (Sunnyvale, CA)
- …joining Meta 8. Experience with ASIC development cycle. 9. Experience in Verilog, SystemVerilog , C/C++ based verification and UVM methodology. 10. Experience ... the entire stack, from transistor, through architecture, to firmware, and algorithms.As a Design Verification Engineer at Meta Reality Labs, you will work with… more
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