• UVM / SystemVerilog Design…

    US Tech Solutions (Goleta, CA)
    …and AXI to driven the internal components and send data. **Responsibilities** + As a UVM / SystemVerilog Design Verification Engineer, you will own ... **Job Description:** + The project relates to the design and verification of a custom...with verification methodologies and languages such as UVM and SystemVerilog . + Experience developing and… more
    US Tech Solutions (02/08/25)
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  • Senior Design Verification Engineer,…

    Google (Mountain View, CA)
    …5 years of experience with verification methodologies and languages such as UVM and SystemVerilog . + Experience developing and maintaining verification ... scenarios. + Create and enhance constrained-random verification environments using SystemVerilog and Universal Verification Methodology ( UVM ) or verify… more
    Google (03/28/25)
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  • ASIC Engineer, Design Verification

    Meta (Sacramento, CA)
    … verification . 10. 10+ years experience in IP/sub-system and/or SoC level verification based on SystemVerilog UVM /OVM based methodologies. 11. Experience ... responsible for the verification closure of a design module or sub-system from test-planning, UVM based test bench development to verification closure.… more
    Meta (04/18/25)
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  • ASIC Engineer, Design Verification

    Meta (Sunnyvale, CA)
    …in IP/sub-system and/or SoC level verification based on SystemVerilog UVM /OVM based methodologies 11. Experience with Design verification of ... responsible for the verification closure of a design module or sub-system from test-planning, UVM ...development cycles 9. 14+ years of hands-on experience in SystemVerilog / UVM methodology and/or C/C++ based verification… more
    Meta (03/19/25)
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  • ASIC Engineer, Design Verification

    Meta (Sunnyvale, CA)
    …ASIC development cycles 9. 3+ years experience in block/IP/sub-system and/or SoC level verification based on SystemVerilog UVM /OVM based methodologies 10. ... responsible for the verification closure of a design module or sub-system from test-planning, UVM ...to joining Meta. 7. 3+ years hands-on experience in SystemVerilog / UVM methodology or C/C++ based verification… more
    Meta (03/08/25)
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  • ASIC Engineer, Design Verification

    Meta (Sunnyvale, CA)
    …development cycles. 10. 5+ years of experience in IP/sub-system and/or SoC level verification based on SystemVerilog UVM /OVM based methodologies. 11. ... responsible for the verification closure of a design module or sub-system from test-planning, UVM ...practical experience. 8. 5+ years of hands-on experience in SystemVerilog / UVM methodology and/or C/C++ based verification… more
    Meta (02/04/25)
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  • ASIC Design Verification Engineer,…

    Google (Sunnyvale, CA)
    …+ Master's degree or PhD in Electrical Engineering. + 6 years of experience in design verification . + Experience with UVM (Universal Verification ... and its integration within AI/ML-driven systems. As an ASIC Design Verification Engineer, you will be part...+ Create a constrained-random verification environment using SystemVerilog and Universal Verification Methodology ( UVM… more
    Google (04/18/25)
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  • Design Verification Engineer

    Meta (San Diego, CA)
    … UVM methodology. 9. 3+ years experience in IP/sub-system and/or SoC level verification based on SystemVerilog UVM /OVM based methodologies. 10. Experience ... transistor, through architecture, to firmware, and algorithms. As a Design Verification Engineer at Meta Reality Labs,...13. Experience in development of UVM based verification environments from scratch. 14. Experience with Design… more
    Meta (04/09/25)
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  • Principal / Senior Principal Digital…

    Northrop Grumman (Mcclellan, CA)
    …SystemVerilog ). Experience with SystemVerilog Assertions (SVA) and Universal Verification Methodology ( UVM ) is required. Successful candidates will have ... + Experience with SystemVerilog Assertions (SVA) + Knowledge of Universal Verification Methodology ( UVM ) + Experience with scripting languages (Bash, Perl,… more
    Northrop Grumman (04/30/25)
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  • Silicon Design Verification…

    Google (Mountain View, CA)
    …3 years of experience with verification methodologies and languages such as UVM and SystemVerilog . + Experience in developing and maintaining verification ... an emphasis on computer architecture. + Experience in low-power design verification . Be part of a team...and enhance constrained random verification environments using SystemVerilog and Universal Verification Methodology ( UVM… more
    Google (04/02/25)
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