- US Tech Solutions (Goleta, CA)
- …and AXI to driven the internal components and send data. **Responsibilities** + As a UVM / SystemVerilog Design Verification Engineer, you will own ... **Job Description:** + The project relates to the design and verification of a custom...with verification methodologies and languages such as UVM and SystemVerilog . + Experience developing and… more
- Meta (Sunnyvale, CA)
- … verification 8. 2+ years experience in block/IP/sub-system and/or SoC level verification based on SystemVerilog UVM /OVM based methodologies 9. Experience ... responsible for the verification closure of a design module or sub-system from test-planning, UVM based test bench development to verification closure.… more
- Meta (Sacramento, CA)
- … verification 10. 8+ years experience in IP/sub-system and/or SoC level verification based on SystemVerilog UVM /OVM based methodologies 11. Experience ... responsible for the verification closure of a design module or sub-system from test-planning, UVM based test bench development to verification closure.… more
- Meta (Sunnyvale, CA)
- … verification 9. 6+ years of experience in IP/sub-system and/or SoC level verification based on SystemVerilog UVM /OVM based methodologies 10. Experience ... responsible for the verification closure of a design module or sub-system from test-planning, UVM based test bench development to verification closure.… more
- Meta (Sunnyvale, CA)
- … UVM methodology 10. 2+ years experience in IP/sub-system and/or SoC level verification based on SystemVerilog UVM /OVM based methodologies 11. Experience ... transistor, through architecture, to firmware, and algorithms. As a Design Verification Engineer at Meta Reality Labs,...or a related field 18. Experience in development of UVM based verification environments from scratch 19.… more
- Amazon (Sunnyvale, CA)
- … engineer. Create UVM verification simulation solutions. The FPGA verification engineer will work with FPGA design and systems teams to define ... legacy constraints. The FPGA verification engineer will work with design and systems teams to define/develop/implement/test/release UVM test environments in… more
- Amazon (Sunnyvale, CA)
- …working with design engineers and architects - Create and enhance constrained-random verification environments using SystemVerilog and UVM and write SVA. ... What will you help us create? As a Sr. Design Verification Engineer at Amazon, you will...CS. - 7+ years of hands-on experience in Verilog, SystemVerilog , C/C++ based verification and UVM… more
- Capgemini (Santa Clara, CA)
- …Engineering or equivalent, with 7 years of experience in pre-silicon design verification . + Expertise in SystemVerilog , UVM , and SV Assertions, with ... to deliver high-quality silicon solutions. **Your role** + Architect and implement scalable verification environments using SystemVerilog and UVM for IP and… more
- Amazon (Sunnyvale, CA)
- …working with design engineers and architects Create and enhance constrained-random verification environments using SystemVerilog and UVM Write tests in ... CE, or CS 10+ years or more of practical semiconductor design verification experience including System Verilog, UVM , assertions and coverage driven … more
- Google (Mountain View, CA)
- …in low-power design verification . + Experience with Universal Verification Methodology ( UVM ), SystemVerilog , or other scripting languages such ... verification methodologies and languages such as Universal Verification Methodology ( UVM ) and SystemVerilog ....and ensure documentation is easy to use. + Perform design verification for future CPU developments. +… more
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