• Principal Digital Design Engineer

    Renesas (Duluth, GA)
    …Job Description + Propose, architect, and design RTL in Verilog for use in a mixed - signal integrated circuit + Contribute as part of a highly experienced team of ... field, with minimum 12+ years of experience + 8+ years of direct experience in ASIC/ IC design with deep knowledge of the entire IC design flow + Experience… more
    Renesas (12/12/25)
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