• CPU Cache Subsystem…

    Google (Poughkeepsie, NY)
    … memory subsystem design . + 10 years of experience in high-performance CPU , cache subsystem or AI accelerator logic/RTL design including ... . + Lead and manage a team of design engineers working on CPU , cache subsystem , or AI accelerator design and integration into SoC, emphasizing… more
    Google (06/21/25)
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  • CPU Arithmetic Dataflow Design…

    Google (Poughkeepsie, NY)
    …+ 10 years of experience in high-performance CPU , cache subsystem or AI accelerator logic/RTL design including microarchitecture definition and PPA ... . + Lead and manage a team of design engineers working on CPU , cache subsystem , or Artificial Intelligence (AI) accelerator design and integration… more
    Google (06/21/25)
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  • Quantum Verification Engineer

    IBM (Poughkeepsie, NY)
    …for the pre-silicon functional and performance verification of our chipsets, covering the CPU core, cache /nest subsystem , memory hierarchy, and other ... and problem debug. Verification is performed at various levels within the design hierarchy. A background in Computer Engineering or Electrical Engineering with… more
    IBM (05/22/25)
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