• UVM Verification Engineer

    Actalent (Dallas, TX)
    FPGA UVM Verification Engineer Job Description We are seeking a skilled FPGA UVM Verification Engineer with a strong experience in networking to ... join our innovative team. The FPGA Verification Engineer will be responsible for developing...on networking applications. This role requires expertise in Universal Verification Methodology ( UVM ) and a solid understanding… more
    Actalent (05/31/25)
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  • ASIC Engineer , Design Verification

    Meta (Austin, TX)
    **Summary:** Meta is hiring ASIC Design Verification Engineer within the Infrastructure organization. We are looking for individuals with experience in Design ... On Chip (SoC) for data center applications.As a Design Verification Engineer , you will be part of...closure of a design module or sub-system from test-planning, UVM based test bench development to verification … more
    Meta (05/06/25)
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  • ASIC Engineer , Design Verification

    Meta (Austin, TX)
    **Summary:** Meta is hiring ASIC Design Verification Engineer within the Infrastructure organization. We are looking for individuals with experience in Design ... On Chip (SoC) for data center applications.As a Design Verification Engineer , you will be part of...closure of a design module or sub-system from test-planning, UVM based test bench development to verification … more
    Meta (04/18/25)
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  • ASIC Engineer , Design Verification

    Meta (Austin, TX)
    **Summary:** Meta is hiring ASIC Design Verification Engineer within the Infrastructure organization. We are looking for individuals with experience in Design ... On Chip (SoC) for data center applications.As a Design Verification Engineer , you will be part of...closure of a design module or sub-system from test-planning, UVM based test bench development to verification … more
    Meta (03/09/25)
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  • Silicon Verification Engineer

    ManpowerGroup (Austin, TX)
    Our client, a leader in technology innovation, is seeking a Silicon Verification Engineer to join their team. As a Silicon Verification Engineer , you ... mindset which will align successfully in the organization. **Job Title:** Silicon Verification Engineer **Location:** Austin, TX **What's the Job?** + Focus… more
    ManpowerGroup (05/21/25)
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  • Design Verification Engineer

    Meta (Austin, TX)
    …entire stack, from transistor, through architecture, to firmware, and algorithms. As a Design Verification Engineer at Meta Reality Labs, you will work with a ... of the art IPs or SoCs. **Required Skills:** Design Verification Engineer Responsibilities: 1. Work with researchers...years of hands-on experience in Verilog, SystemVerilog, C/C++ based verification and UVM methodology. 9. 3+ years… more
    Meta (05/14/25)
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  • Design Verification Engineer

    Meta (Austin, TX)
    …the entire stack, from transistor, through architecture, to firmware, and algorithms.As a Design Verification Engineer at Meta Reality Labs, you will work with a ... cases for multiple state of the art IPs. **Required Skills:** Design Verification Engineer Responsibilities: 1. Work with researchers and architects defining… more
    Meta (05/07/25)
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  • Senior SOC Pre-Silicon Verification…

    Micron Technology, Inc. (Richardson, TX)
    …how the world uses information to enrich life. As an HBM SOC Pre-Silicon Verification Engineer , you will be responsible for the design & development of ... Logic chip can use a full ASIC flow. Lastly, verification and testing (validation) of HBM is the most...Ability to develop validation environments using System Verilog and UVM . + Ability to write tests using UVM… more
    Micron Technology, Inc. (04/19/25)
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  • Design Verification Engineer…

    Meta (Austin, TX)
    …the entire stack, through algorithms to architecture, transistors to firmware. As a Design Verification Engineer at Meta's Reality Labs, you will work with a ... multiple state of the art machine learning IPs. **Required Skills:** Design Verification Engineer - Machine Learning Accelerators Responsibilities: 1. Work with… more
    Meta (05/17/25)
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  • ASIC Design Verification Engineer

    Qualcomm (Austin, TX)
    …for digital power IP's, its testbench development using the advanced verification methodology such as SystemVerilog- UVM , coverage development, assertion model ... connected future for all. The team is responsible for the complete verification lifecycle, from system-level concept to tape out and post-silicon support. The… more
    Qualcomm (04/09/25)
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