- IBM (Rochester, MN)
- …. Comprehensive understanding of Microprocessor, ASIC , Signal and Power Integrity, 1st Level Chip Packaging , and hardware development engineering ... channels and Power Distribution Networks . Familiarity with Microprocessor and ASIC 1st Level Chip Packaging and Hardware Development . Demonstrated… more
- Qualcomm (San Diego, CA)
- …designers at various levels to help with designing high-speed, high-performance and low- power mixed- signal IPs (SerDes, DDR, PLL, DAC, ADC, sensors, etc.) ... targeted for 5G, AI/ML, compute, and automotive applications. QCT mixed- signal design team consists of architects and ASIC...our annual bonus). In addition, our highly competitive benefits package is designed to support your success at work,… more
- Qualcomm (San Diego, CA)
- …integrated circuit designers at various levels to help with designing high-performance and low- power mixed- signal IPs (SerDes, DDR, PLL, DAC, ADC, sensors, etc.) ... Technologies, Inc. **Job Area:** Engineering Group, Engineering Group > Analog Mixed Signal Design **General Summary:** QCT Mixed- Signal IP (MSIP) design team… more
- Meta (Menlo Park, CA)
- **Summary:** Meta is looking for an experienced ASIC Packaging Engineer, Signal Integrity, and Power Integrity focus for its ASIC packaging team ... custom Silicon for Infrastructure as well as to develop packaging solutions that are optimal for our ASIC...Responsibilities: 1. Drive chip- package -system co-design by driving signal and power integrity requirements analysis and… more
- Cisco (San Jose, CA)
- …custom library development (Standard Cell and I/O), physical design & DFT, Signal Integrity, and complexed packaging technology. Our silicon is developed ... ASIC Engineer II (Co-Op) United States Apply (https://jobs.cisco.com/jobs/Login?projectId=1426575)...Relevant courses include Computer Architecture, Logic Design, VLSI, Programming, Signal and Power Integrity, and DFx. +… more
- Qualcomm (San Diego, CA)
- …Summary:** Qualcomm mixed- signal IP design team is seeking talented senior ASIC digital designers to join our efforts in developing the next generation of ... - Apply computer architecture and optimization techniques for improving power , performance, and area of the IPs - Assist...- Assist in running the full suite of front-end ASIC design tools (lint checking, CDC, DFT, synthesis, FV,… more
- Broadcom (San Jose, CA)
- …, area, and speed. - Understanding of complex issues related to timing closure, power integrity and signal integrity. - Physical verification to ensure error ... industry, including AI. Be part of the Design Implementation team within Broadcom ASIC Products Division where we create CMOS ASIC 's for industry leading… more
- Amazon (Cupertino, CA)
- …to Global 500 companies trust our robust suite of products and services to power their businesses. Diverse Experiences AWS values diverse experiences. Even if you do ... scale and rapid integration of emergent technologies. We're looking for an ASIC Design Eengineer to help us trail-blaze new technologies and architectures, while… more
- Broadcom (San Jose, CA)
- …including synthesis, design for test, floorplanning, place and route, clock methodology, power planning and analysis, timing closure, signal integrity and ... please Sign-In before you apply.** **Job Description:** **Job Description:** + ASIC implementation engineer with demonstrated expertise in multiple disciplines… more
- Lockheed Martin (King Of Prussia, PA)
- …products & insertion opportunities\. **Who You Are** We are seeking a highly skilled ASIC & FPGA Design Engineer to join our team in developing and deploying Radar ... and other FPGA development tools \- Develop and optimize algorithms for signal processing, image processing, and machine learning acceleration on FPGAs \-… more
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