• ASIC Power Efficiency…

    Google (Sunnyvale, CA)
    …measuring chip power consumption. + Develop design improvements to increase power efficiency . + Collaborate with cross-functional teams in defining power ... using EDA tools such as PTPX, PowerArtist, or PrimePower. + Experience driving power - efficiency improvement in chip designs. + Experience with pre-silicon vs… more
    Google (06/17/25)
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  • Senior ASIC Power Engineer

    NVIDIA (Santa Clara, CA)
    We are now looking for a Senior ASIC Power Engineer ! NVIDIA is seeking extraordinary power engineers to design hardware accelerators and processors on ... to extend the state of the art performance and efficiency + You are expected to understand the design...are expected to understand the design and implementation, develop power metrics and drive power reductions +… more
    NVIDIA (04/23/25)
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  • ASIC Design Efficiency…

    NVIDIA (Santa Clara, CA)
    We are now looking for an ASIC Design Efficiency Engineer . NVIDIA is seeking extraordinary methodology engineers to design hardware accelerators and ... and system designs to extend the state of the art performance and efficiency . + Understand the design and implementation, develop methodology and infrastructure to… more
    NVIDIA (06/27/25)
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  • ASIC Rtl Design Engineer

    Google (Sunnyvale, CA)
    …will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency , and integration. As a Design Engineer , you will play ... + Experience with industry-standard EDA tools for simulation, synthesis, and power analysis. Preferred qualifications: + Master's degree or PhD in Electrical… more
    Google (07/01/25)
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  • ASIC SoC System Level Test Engineer

    Google (Sunnyvale, CA)
    …with System Level Test (SLT) or product engineering. + Experience with ASIC or SoC prototype bring-up, debug, functional verification or functional manufacturing ... team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to...use Google services around the world. We prioritize security, efficiency , and reliability across everything we do - from… more
    Google (07/09/25)
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  • SoC Power /Performance Post-Si Validation…

    Qualcomm (San Diego, CA)
    …one or more commercially available emulation platforms and deep familiarity with ASIC power estimation, analysis, and optimization, as well as industry-standard ... Group > ASICS Engineering **General Summary:** As a SoC Power /Performance Post-Si Validation & Emulation Engineer , you...efficiency , and performance for various emulation platforms for power measurements. + Perform power , thermal, and… more
    Qualcomm (06/04/25)
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  • Senior Power Architecture and Optimization…

    NVIDIA (Santa Clara, CA)
    …power data, and driving ASIC teams to improve their units' power efficiency ; and is responsible for researching, developing, and deploying methodologies ... We are now looking for a Senior Power Architecture and Optimization Engineer ! NVIDIA... power analysis tools, to help improve product power efficiency . + Develop and share best… more
    NVIDIA (06/17/25)
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  • Senior Emulation Power Engineer

    NVIDIA (Santa Clara, CA)
    …power data and driving ASIC teams to improve their units' power efficiency ; and is responsible for researching, developing, and deploying methodologies to ... We are looking for a Senior Emulation Power Engineer ! NVIDIA prides in having...concepts of energy consumption, estimation, data movement and low power design. + Familiarity with Verilog and ASIC… more
    NVIDIA (05/29/25)
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  • Server Chipset Power Engineer

    Qualcomm (Austin, TX)
    …are highly optimized for the needs of the server product. **Position: Server Chipset Power Engineer ** We are seeking a highly experienced Server Chipset Power ... innovative solutions that push the limits of performance, energy efficiency , and scalability. Our focus is on developing server-class... and silicon/system limits + Strong fundamentals in digital ASIC design and power of CMOS circuits… more
    Qualcomm (05/09/25)
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  • Package Design Engineer

    Meta (Menlo Park, CA)
    **Summary:** Meta is looking for an experienced ASIC Packaging Engineer , Signal Integrity, and Power Integrity focus for its ASIC packaging team to ... to develop packaging solutions that are optimal for our ASIC roadmap. We are building a competency in Packaging...such as 2.5D/3D and heterogeneous integration to improve bandwidth, power efficiency and package form factor for… more
    Meta (06/28/25)
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