- Qualcomm (San Diego, CA)
- …Inc. Job Area: Engineering Group, Engineering Group > ASICS Engineering General Summary: As a Timing Engineer , you will play a vital role in Timing analysis ... PT/PT-SI and Tempus. You will facilitate and drive STA methodology for Qualcomm using PT-SI, Tempus and best in...off for complex SOC's. Hands on contribution for STA timing sign off. A timing Engineer… more
- Qualcomm (San Diego, CA)
- …is part of the Global SOC organization and is responsible for STA methodology and signoff, foundry technology enablement and analysis, design automation and internal ... EDA tools, design analysis and optimization tools and platforms, low power architecture, methodology , and IP, and foundation IP development. About the Role As a… more
- Theconstructsim (Milpitas, CA)
- …insurance Paid time off Relocation bonus Vision insurance Job Title: Front-End ASIC Design Engineer - Milpitas, CA Responsibilities Support customer's design ... through all phases of ASIC execution at Socionext. Ensure designs meet product Performance‑Power‑Area‑Schedule requirements. Tasks may include Architecture /… more
- Hewlett Packard Enterprise Development LP (San Jose, CA)
- ASIC Engineer Sr StaffThis role has been designed as 'Hybrid' with an expectation that you will work on average 2 days per week from an HPE office.**Who We ... for next-generation networking platforms. We are looking for a seasoned**Design-for-Test (DFT) Engineer ** to join our team and contribute to the development of… more
- Eridu Corporation (San Francisco, CA)
- … simulations: collaborate with the team to execute comprehensive gate-level simulations, including timing and power analysis, to validate the ASIC design before ... fabrics, leveraging your extensive experience in networking. Technical Expertise in ASIC Verification:Provide technical leadership in the verification of complex … more
- Intel Corporation (Santa Clara, CA)
- # **Welcome!**## .Senior Design Engineer - AI SoC Development page is loaded## Senior Design Engineer - AI SoC Developmentlocations: US, California, Folsom: US, ... applications, from edge devices to data center accelerators. If you are an engineer with strong technical and communication skills who thrives in a fast-paced… more
- Theconstructsim (Milpitas, CA)
- Pre-layout STA to ascertain feasibility, timing constraint validation and feedback to customers and design teams Chip/Block Level Floorplanning and pin assignment ... completeness and feasibility Handle all the Physical design tasks (Placement, Timing Optimization, Clock Tree Synthesis, Routing) Perform sign-off tasks (RC… more
- Advanced Micro Devices (Santa Clara, CA)
- …with global Front-End design team and physical design team for large scale ASIC chip physical implementation Drive design and methodology improvements across ... interfaces such as AHB, AXI and various standard peripherals & interfaces is required ASIC DV experience in reusable verification methodology such as UVM Have… more
- Renesas Electronics Corporation (San Francisco, CA)
- …and lab debug is a plus. Fluent in either Verilog RTL coding and ASIC design methodology . Competence in developing design constraints for synthesis, STA and ... ensure spec compliance. Cover digital backend design from synthesis, upf, static timing analysis and logic equivalent checking. Interface with P&R for digital… more
- NVIDIA Corporation (Santa Clara, CA)
- We are now looking for a Senior Signal & Power Integrity Engineer !NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 ... improvements of SI models using data from lab measurements and/or modelling tool/ methodology updates.* Substrate and board layout SI guidelines creation, review and… more
