- Google (Mountain View, CA)
- … memory subsystem design . + 10 years of experience in high-performance CPU , cache subsystem or AI accelerator logic/RTL design including ... . + Lead and manage a team of design engineers working on CPU , cache subsystem , or AI accelerator design and integration into SoC, emphasizing… more
- Google (Mountain View, CA)
- …+ 10 years of experience in high-performance CPU , cache subsystem or AI accelerator logic/RTL design including microarchitecture definition and PPA ... . + Lead and manage a team of design engineers working on CPU , cache subsystem , or Artificial Intelligence (AI) accelerator design and integration… more
- Qualcomm (San Diego, CA)
- …Next Generation, High-Speed, Memory and Cache Controller and Advanced Memory NoCs based Subsystem Design Team is looking for ASIC Design Engineers for ... DSP, and multimedia processors + On-chip tightly coupled SRAM & L3 cache controller architecture/ design + Experience with x86 or ARM CPU /bus architectures +… more
- Qualcomm (Santa Clara, CA)
- …CPU and SOC level micro-architectures. You will work on a selected part of the CPU Design Verification to ensure that it functions to the standards of being ... Qualcomm Technologies, Inc. **Job Area:** Engineering Group, Engineering Group > CPU Engineering **General Summary:** As a Design Verification Engineer,… more
- Qualcomm (San Diego, CA)
- …IP Team consists of a multi-disciplinary group involved in the definition and design of Platform infrastructure HW components such as Memory controllers, System ... cache , System MMU and Interconnect that are implemented in...using simulation; Ability to partner effectively with IP designers, Design Verification teams and System performance architects. Key Deliverables:… more
- Qualcomm (Boxborough, MA)
- …pipelines, memory subsystem and interconnect, and power and system level design Identify advanced ways to optimize hardware design for better performance, ... solutions. **What you will be doing** : Micro-architect and design RTL for blocks and modules of Adreno GPU...is desired. . Experience in designing RTL for GPU, CPU , DSP, Machine-Learning, cache , controller, video, display,… more
- Google (Mountain View, CA)
- …(PPA) under peak current and thermal constraints with a focus on the CPU subsystem . + Define power key performance indicators and SoC/IP-level power ... and power analysis. + 8 years of experience in SoC power management or low power design /methodology. + Experience in CPU power in mobile SoCs from CPU … more
- IBM (Austin, TX)
- …for the pre-silicon functional and performance verification of our chipsets, covering the CPU core, cache /nest subsystem , memory hierarchy, and other ... and problem debug. Verification is performed at various levels within the design hierarchy. A background in Computer Engineering or Electrical Engineering with… more