• Qualcomm (Boxborough, MA)
    …pipelines, memory subsystem and interconnect, and power and system level design Identify advanced ways to optimize hardware design for better performance, ... solutions. What you will be doing : Micro-architect and design RTL for blocks and modules of Adreno GPU...languages is desired. *Experience in designing RTL for GPU, CPU , DSP, Machine-Learning, cache , controller, video, display,… more
    Upward (07/21/25)
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  • CPU Cache Subsystem…

    Google (Portland, OR)
    … memory subsystem design . + 10 years of experience in high-performance CPU , cache subsystem or AI accelerator logic/RTL design including ... . + Lead and manage a team of design engineers working on CPU , cache subsystem , or AI accelerator design and integration into SoC, emphasizing… more
    Google (07/02/25)
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  • Next-Gen, High-Speed Memory Subsystem ASIC…

    Qualcomm (San Diego, CA)
    …Next Generation, High-Speed, Memory and Cache Controller and Advanced Memory NoCs based Subsystem Design Team is looking for ASIC Design Engineers for ... DSP, and multimedia processors + On-chip tightly coupled SRAM & L3 cache controller architecture/ design + Experience with x86 or ARM CPU /bus architectures +… more
    Qualcomm (05/20/25)
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  • CPU Verification Engineer (Multiple…

    Qualcomm (Santa Clara, CA)
    …CPU and SOC level micro-architectures. You will work on a selected part of the CPU Design Verification to ensure that it functions to the standards of being ... Qualcomm Technologies, Inc. **Job Area:** Engineering Group, Engineering Group > CPU Engineering **General Summary:** As a Design Verification Engineer,… more
    Qualcomm (07/04/25)
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  • Memory Subsystem Performance Architect

    Qualcomm (San Diego, CA)
    …IP Team consists of a multi-disciplinary group involved in the definition and design of Platform infrastructure HW components such as Memory controllers, System ... cache , System MMU and Interconnect that are implemented in...using simulation; Ability to partner effectively with IP designers, Design Verification teams and System performance architects. Key Deliverables:… more
    Qualcomm (07/18/25)
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  • Custom SOC IP Verification Engineer

    NVIDIA (Santa Clara, CA)
    …interconnects (AXI, ACE, CHI). You will play a key role in verifying the cache protocol compliance and ensuring coherency across CPU and GPU memory subsystems, ... 8+ years of experience in ASIC verification, particularly in cache coherency or memory subsystem verification. +...etc. + Familiarity with SoC architectures, memory models, and CPU - cache interactions. + Proficiency in scripting languages… more
    NVIDIA (06/27/25)
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  • Senior Silicon Logic Design Engineer

    Microsoft Corporation (Raleigh, NC)
    …+ 4+ years logic design experience as a part of either CPU , Cache , Fabric, Compute Tile, Digital Power Management, PCMs, Debug, Peripherals and/or ... Design Team, contributing to micro-architecture implementation, RTL coding, IP and subsystem development, and SoC integration, along with design quality… more
    Microsoft Corporation (07/18/25)
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