- Apple Inc. (Sunnyvale, CA)
- A leading technology company is seeking a Cellular SoC Static Timing Analysis Engineer to ensure precision in timing for chip design. Candidates should ... have strong knowledge of ASIC timing constraints, proficiency in tools like Synopsys PrimeTime, and excellent communication skills. The base pay range is between… more
- Apple Inc. (San Diego, CA)
- A leading technology company is seeking a Cellular SoC Static Timing Analysis Engineer to ensure optimal timing performance for Apple's chip designs. The ... successful candidate will perform static timing analysis, generate constraints, and collaborate with various teams to resolve timing issues. Required… more
- Apple Inc. (San Diego, CA)
- Cellular SoC Static Timing Analysis...the entire project. Generation of block and full chip timing constraints. Own timing sign ‑off to ... Engineer, you will have responsibilities spanning various aspects of SOC design: Full chip and block level timing...methodologies and flows. Experience in reducing the number of timing sign ‑off corners by merging different … more
- Apple Inc. (Sunnyvale, CA)
- Cellular SoC Static Timing Analysis...the entire project. Generation of block and full chip timing constraints. Own timing sign -off to ... Engineer, you will have responsibilities spanning various aspects of SOC design: Full chip and block level timing...with RTL, synthesis, and physical design teams to resolve timing issues. Own STA sign -off for block… more
- Broadcom (Fort Collins, CO)
- …user, please create your candidate login account before you apply for a job. (Click Sign In > Create Account)** **2. If you already have a Candidate Account, please ... Sign -In before you apply.** **Job Description:** Be part of...engineering group developing custom CMOS ASICs for cutting-edge AI, Cellular , Networking, Computing, and Storage products. This position offers… more
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