• Design Verification ( DV

    Cisco (San Jose, CA)
    Design Verification ( DV ) Engineer Apply (https://jobs.cisco.com/jobs/Login?projectId=1451624) + Location:San Jose, California, US + Area of ... Verification teams and Architects to understand chip architecture and drive design verification requirements. You'll work with SDK and Software teams as part… more
    Cisco (10/14/25)
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  • ASIC Design Verification

    Amazon (Austin, TX)
    …technologies. In this role you will: . Implement a state of the art verification environment to facilitate testing of the RTL against reference Matlab/C models . ... be reused for the ASIC implementation . Run formal verification of complex blocks to ensure functional correctness ....blocks to ensure functional correctness . Work with the design and communication systems team and participate in system… more
    Amazon (08/14/25)
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  • GenAI software Development Engineer

    Micron Technology, Inc. (San Jose, CA)
    …models (LLMs) for the purpose of automated Silicon design and Design Verification ( DV ). The engineer is expected to build LLM based EDA workflows ... and greater quality. **Responsibilities:** + Develop LLM applications to automate electronics design and verification . + Optimize and fine-tune LLMs for the… more
    Micron Technology, Inc. (09/13/25)
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  • ASIC/SOC DV Engineer (Silicon…

    SpaceX (Sunnyvale, CA)
    …to work extended hours and weekends as needed COMPENSATION AND BENEFITS: Pay range: Design Verification Engineer /Level I: $130,000.00 - $155,000.00/per year ... ASIC/SOC DV Engineer (Silicon Engineering) Sunnyvale, CA Apply...Design Verification Engineer /Level II: $150,000.00 - $180,000.00/per year Your… more
    SpaceX (09/19/25)
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  • Design Verification Engineer

    Amazon (Sunnyvale, CA)
    …to contribute to a groundbreaking new system with few legacy constraints. The FPGA verification engineer will work with design and systems teams to ... Enhance your leadership skills while contributing to a dynamic DV team * Create reusable Verification IP...verification simulation solutions. The FPGA verification engineer will work with FPGA design and… more
    Amazon (10/04/25)
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  • AMS Design Verification

    Texas Instruments (Dallas, TX)
    …on some of TI's most advanced custom products. As an AMS DV Engineer , you will have responsibility for driving design execution excellence across the company ... projects for TI's largest customer. You'll work closely with design , systems, verification , characterization, test and product...and rewarding opportunity. In this role as an AMS DV Engineer your responsibilities will include: *… more
    Texas Instruments (09/05/25)
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  • Senior Principal Design Verification

    BAE Systems (San Diego, CA)
    …may be available based on position level and/or job specifics. **Senior Principal Design Verification Engineer - FPGA - (Sign-on Bonus)** **117193BR** ... career. BAE is looking for experienced senior level FPGA Design Verification Engineers who can plan, architect,...your leadership skills while leading small to medium sized DV teams + Create reusable Verification IP… more
    BAE Systems (10/10/25)
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  • Sr Staff Design Verification

    Renesas (Austin, TX)
    Sr Staff Design Verification Engineer Job Description * Plan the verification of complex SoC & design blocks by fully understanding the design ... routines to run on embedded MC Company Description Renesas is seeking a SoC/IP Verification Engineer for our Infrastructure Power team in Austin, TX, where we… more
    Renesas (10/13/25)
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  • Staff ASIC Design Verification

    Google (Mountain View, CA)
    Staff ASIC Design Verification Engineer , Platforms and Devices _corporate_fare_ Google _place_ Mountain View, CA, USA **Advanced** Experience owning outcomes ... scripting languages, Software (SW) development frameworks and their impact on Design Verification ( DV ). + Experience creating and using verification more
    Google (10/01/25)
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  • SystemVerilog/UVM Design

    US Tech Solutions (Goleta, CA)
    …Months** **Job Description:** + We are seeking a highly skilled and meticulous SystemVerilog/UVM Design Verification Test Engineer to play a crucial role in ... (Required):** + 3+ years of professional experience specifically in IC/SOC Design Verification ( DV ). + Mandatory expert-level proficiency in SystemVerilog… more
    US Tech Solutions (10/14/25)
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