- Google (Mountain View, CA)
- Memory System Architect , Silicon _corporate_fare_ Google _place_ Mountain View, CA, USA **Mid** Experience driving progress, solving problems, and ... one or more of these areas, Coherent Interconnects, Caches, Memory Systems . + Knowledge of Hardware Description...will participate in the development of technology in the memory system and filing associated patents. Google's… more
- Google (Mountain View, CA)
- Display Silicon Architect _corporate_fare_ Google _place_ Mountain View, CA, USA **Advanced** Experience owning outcomes and decision making, solving ambiguous ... or equivalent practical experience. + 6 years of experience working in display-related silicon chip design, with digital, analog, and IC designs. + Experience with… more
- Google (Mountain View, CA)
- SoC Power Architect , Devices and Services, Silicon _corporate_fare_ Google _place_ Mountain View, CA, USA; San Diego, CA, USA **Advanced** Experience owning ... computer architecture, performance and power analysis. + Experience with system -level power modeling, optimizations and analysis for one or...for one or more major SoC subsystems such as memory path, multimedia, etc. + Excellent written and verbal… more
- NVIDIA (Santa Clara, CA)
- …+ Developing architecture and micro-architecture to improve the state-of-the-art in GPU memory system , Memory management, Virtualization & security ... while optimizing performance, area, complexity, and power on leading-edge silicon processes. This GPU memory architecture team...performance and functional issues with high-level models, RTL simulation, silicon & systems . What we need to… more
- NVIDIA (Santa Clara, CA)
- …Engineering, Physics (or equivalent experience). + 15+ years of experience in DRAM or memory system architecture, with at least 5+ years focused on HBM ... NVIDIA is seeking a world-class Principal DRAM Architect to define, drive, and deliver the architecture,...architecture, roadmap, and implementation of next-generation AI and graphics memory solutions! This role sits at the intersection of… more
- NVIDIA (Santa Clara, CA)
- …issues with high-level models, RTL simulation and emulation, silicon , and systems . + Collaborate with outside partners on system infrastructure. What we ... have a strong track record of understanding and analyzing memory systems architecture to improve performance per...processor and system architectures, focusing on the memory system and energy efficiency. + Develop… more
- Meta (Austin, TX)
- …of the system , including kernel, synchronization primitives, resource allocators, memory management, security, I/O systems , persistence, etc 2. Develop ... Engineer, you'll have the opportunity to design, develop, and optimize embedded firmware systems for our AR, VR, and wearable devices, working on low-level … more
- NVIDIA (Santa Clara, CA)
- …prototyping, use case analysis, and system -level cost/benefit tradeoff. + Architect , design, and integrate memory system -level features, controllers, ... professional solution markets. Prior experience in the lab with system -level post- silicon bring-up and debug is highly...desired. What you'll be doing: + Build roadmaps of memory system -level features to address low power,… more
- Advanced Micro Devices, Inc (Austin, TX)
- …of AI and beyond. Together, we advance your career. PRINCIPAL EPYC CUSTOMER PLATFORM ARCHITECT / SYSTEMS DESIGNER THE ROLE: It's a pivotal role where you draw ... customers and AMD's server business. Work at depth across silicon design, system validation, manufacturing test, firmware,...through to launch. PREFERRED EXPERIENCE: + Deep knowledge of system architecture and design including memory , I/O,… more
- Snap Inc. (Palo Alto, CA)
- …first pair of glasses that bring augmented reality to life. We're looking for a System Power Architect Engineer, Devices to join Team Snap! Working from our ... and model power consumption for a wide array of system loads, including SoCs, CPUs, GPUs, memory ,...power profiles + Early Power Estimation: Extract and integrate pre- silicon power estimates and power breakdown data for chips… more