- CACI International (Denver, CO)
- Network Timing Engineer Job Category: Information Technology Time Type: Full time Minimum Clearance Required to Start: TS/SCI with Polygraph Employee Type: ... an ongoing basis. **Opportunity:** We are seeking an experienced Network Engineer to design, implement, and maintain...missions. The ideal candidate will have advanced knowledge of network protocols, data communication systems, and timing … more
- SpaceX (Irvine, CA)
- …critical deadlines, as needed COMPENSATION & BENEFITS: Pay range: Physical Design STA/ Timing Engineer /Level I: $120,000.00 - $145,000.00/per year Physical Design ... will expand the performance and capabilities of the Starlink network . RESPONSIBILITIES: + Develop/support automated block and full chip...STA/ Timing Engineer /Level II: $140,000.00 - $170,000.00/per year Your actual level… more
- SpaceX (Irvine, CA)
- Sr. SOC/ASIC Timing Signoff & Front-End Implementation Engineer (Silicon Engineering) Irvine, CA Apply SpaceX was founded under the belief that a future where ... goal of enabling human life on Mars. SR. SOC/ASIC TIMING SIGNOFF & FRONT-END IMPLEMENTATION ENGINEER (SILICON...network . RESPONSIBILITIES: + Full chip and block level timing signoff and convergence through timing ecos… more
- NVIDIA (Santa Clara, CA)
- …to amplify human inventiveness and intelligence. We are now looking for a motivated ASIC Timing Engineer to join our dynamic and growing team. If you want to ... from the crowd: + Background in domain specific STA and timing convergence, such as GPUs, CPUs, DPUs/ Network processors, or SOCs + Understanding of DFT logic and… more
- Google (Sunnyvale, CA)
- …field, or equivalent practical experience. + 3 years of experience in static timing (eg, full chip timing signoff ownership, constraint authoring and ... verification, full chip static timing analysis and timing ECO creation, ...from developing our latest TPUs to running a global network , while driving towards shaping the future of hyperscale… more
- Google (Sunnyvale, CA)
- …field, or equivalent practical experience. + 7 years of experience in static timing (ie, full chip timing signoff ownership, constraint authoring and ... verification, full chip static timing analysis and timing ECO creation, ...from developing our latest TPUs to running a global network , while driving towards shaping the future of hyperscale… more
- Diversified (Washington, DC)
- Video Broadcast Network Engineer - Washington DC Washington, DC, USA Req #4098 Friday, May 2, 2025 About Diversified: Diversified is a global leader in audio ... workflows. In this role, you'll design and manage low-latency, high-reliability network infrastructures that support video, audio, comms, and data transport in… more
- Lilly (Indianapolis, IN)
- …Manufacturing. **Position Description and Responsibilities:** The Principal Automation Integration Engineer - API Network Integration will enable information ... role will be focused on supporting sites and projects within the API Network . These systems include (but not limited too) process automation platforms, HMI/SCADA,… more
- Qualcomm (San Diego, CA)
- …+ Apply electrical design expertise to develop Power Distribution Network (PDN) solutions, perform simulation, analysis, and debug. + Conduct power ... complex process flow from high-level design to synthesis, place and route, timing and power use, and verification or similarly for custom circuit design/layout… more
- DISH Network (Littleton, CO)
- …of connectivity by building and enhancing the country's first virtualized, standalone 5G wireless network from scratch. Our network is free of the limitations of ... & 16. + Strong understanding of RF radio operations over eCPRI, CSR, DU/ timing configurations, and latency considerations from gNB to data centers. + Experience with… more