• Physical Design Engineer

    Google (Sunnyvale, CA)
    …of static timing analysis. + Experience leading one or more aspects of physical design or physical design flow/methodology, to successful tape-outs ... field, or equivalent practical experience. + 7 years of experience in static timing (ie, full chip timing signoff ownership, constraint authoring and verification,… more
    Google (04/23/25)
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  • Physical Design Engineer

    Amazon (Austin, TX)
    …member of our start-up like team through excellent collaboration and teamwork with other physical design engineers as well as with the RTL/Arch. teams About the ... Develop & maintain flows for block and full-chip level static timing analysis * Write, debug & validate timing...(examples: PrimeTime, Tempus, or others) - Understanding of ASIC Physical Design from RTL-to-GDSII - Understanding of… more
    Amazon (05/14/25)
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  • Signoff Static Timing Analysis and Spice…

    Qualcomm (San Diego, CA)
    …develop tools and methodologies for accuracy, compute, in close collaboration with Snapdragon Physical Design and Timing teams. Qualcomm is using leading edge ... with spice, version-to-version validation. + Provide solutions to the Snapdragon design teams, analyze their requests, and address their requests through ticket… more
    Qualcomm (03/04/25)
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  • Silicon Physical Design

    Meta (Sunnyvale, CA)
    …PPA (Power, Performance, and area) of the design . **Required Skills:** Silicon Physical Design Engineer Responsibilities: 1. Develop and own physical ... implementation of multi-hierarchy low-power ML Hardware design including physical -aware logic synthesis, floorplan, place and route, static timing analysis,… more
    Meta (03/28/25)
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  • Staff Engineer - HBM SOC Physical

    Micron Technology, Inc. (Richardson, TX)
    …power per bit solutions in the industry! **Position Overview:** Micron is hiring a Staff Engineer - HBM SOC Physical Design ! You will be responsible for ... improving design and flow issues related to physical design , identifying potential solutions, and working... toolset + 1+ years of experience of Synthesis Design Constraints and Static Timing Analysis. **Preferred… more
    Micron Technology, Inc. (05/09/25)
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  • SOC/ASIC Physical Design

    SpaceX (Sunnyvale, CA)
    SOC/ASIC Physical Design Engineer (Silicon Engineering) Sunnyvale, CA Apply SpaceX was founded under the belief that a future where humanity is out exploring ... ultimate goal of enabling human life on Mars. SOC/ASIC PHYSICAL DESIGN ENGINEER (SILICON ENGINEERING)...+ Run, debug, and fix signoff closure issues in static timing analysis (STA), noise, logic equivalency, physical more
    SpaceX (04/15/25)
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  • Sr. SOC/ASIC Physical Design

    SpaceX (Bastrop, TX)
    Sr. SOC/ASIC Physical Design Engineer (Silicon Engineering) Bastrop, TX Apply SpaceX was founded under the belief that a future where humanity is out ... goal of enabling human life on Mars. SR. SOC/ASIC PHYSICAL DESIGN ENGINEER (SILICON ENGINEERING)...+ Run, debug, and fix signoff closure issues in static timing analysis (STA), noise, logic equivalency, physical more
    SpaceX (04/15/25)
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  • Principal Engineer - HBM SOC Design

    Micron Technology, Inc. (Richardson, TX)
    …power per bit solutions in the industry. **Position Overview:** As a **Principal HBM SOC Design and Integration Engineer ** , you will design and develop ... design optimization for performance and low power consumption, including UPF, static timing analysis, synthesis design constraints, and closing timing with… more
    Micron Technology, Inc. (03/21/25)
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  • Senior Physical Design

    NVIDIA (Santa Clara, CA)
    We are now looking for a Senior Physical Design Engineer . NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 ... you'll be doing: + Responsible for all aspects of physical design and implementation of GPU and...assembly and P&R, timing closure. + Craft designs for static timing analysis, power and noise analysis and back-end… more
    NVIDIA (02/19/25)
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  • Design Methodology Engineer

    Qualcomm (San Diego, CA)
    physical -aware timing and IR drop ECO solutions ⦁ Collaborate closely with physical design and timing teams to drive methodologies to optimize power and ... methodologies in die-level IR drop, STA, and power. The engineer should be proficient in static timing...experience with Primetime or Tempus ⦁ In-depth knowledge of physical design , preferably but not limited to… more
    Qualcomm (05/01/25)
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