• Principal Timing / STA…

    Microsoft Corporation (Hillsboro, OR)
    …that will manage and optimize the Cloud infrastructure. We are looking for a ** Principal Timing / STA Engineer ** to join the team. **Responsibilities** ... + Lead the STA methodology development and execution to meet timing closure targets for complex semiconductor designs. + Collaborate with design, implementation,… more
    Microsoft Corporation (07/22/25)
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  • Implementation Timing / STA Design…

    Qualcomm (Santa Clara, CA)
    …all. Qualcomm's SoC Implementation Team is looking for skilled engineers to focus on timing constraints development, power analysis, STA , and timing closure ... in Tcl, Perl, or Python are also desirable. **Job Description: Principal Duties and Responsibilities** + Develop constraints for physical power-aware synthesis,… more
    Qualcomm (07/08/25)
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  • STA Principal Application…

    Cadence Design Systems, Inc. (Austin, TX)
    …and methodologies. . Work on SDC constraints, advanced OCV/SOCV concepts, derates, PBA timing , Distributed and Concurrent STA flows. . Work efficiently with R&D ... impact on the world of technology. Responsibilities; Perform Static timing analysis, glitch, noise analysis using Tempus Signoff tool....and customer to enable various timing analysis & ECO flows including newer advanced technologies.… more
    Cadence Design Systems, Inc. (07/02/25)
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  • Signoff Static Timing Analysis and Spice…

    Qualcomm (San Diego, CA)
    …Electrical Engineering, or related field. Maths minor is a plus. * Deep knowledge of STA features and Timing concepts. + 2-6 years of experience in Signoff ... preferred. ** Principal Duties and Responsibilities:** * Participate to the STA and Cell Characterization flows and features enablement for foundry advanced… more
    Qualcomm (06/03/25)
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  • Principal Digital Engineer

    Renesas (Austin, TX)
    Principal Digital Engineer Job Description Renesas is seeking a talented individual for their memory interface products team. These products primarily serve data ... verification reviews + Oversee digital backend design, including synthesis, static timing analysis, and logic equivalence checking + Create documentation targeting… more
    Renesas (07/18/25)
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  • IC Physical Design Flow, Principal…

    Cadence Design Systems, Inc. (San Jose, CA)
    …Implementation & Signoff including Synthesis, Place and Route, Design Closure, and timing /power signoff + Guide customers on how to best utilize Cadence technologies ... with EDA tools in the IC digital implementation & signoff flows ( STA tools) + Strong STA and SDC debugging abilities are required. + Low power analysis, Clock… more
    Cadence Design Systems, Inc. (07/18/25)
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  • CPU Physical Design - Low Power Signoff…

    Qualcomm (San Diego, CA)
    …to help create a smarter, connected future for all. As a Qualcomm CPU Engineer , you will lead innovative Central Processing Unit (CPU) design efforts that have a ... Skill/Experience: + 2-10 yrs experience in Physical Design and timing signoff for high speed cores. + Should have...in leading block level or chip level Physical Design, STA and PDN activities** . + Work independently in… more
    Qualcomm (06/05/25)
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