- NVIDIA (Austin, TX)
- …and intelligence. The NVIDIA System-On- Chip (SOC) group is looking for a top Senior ASIC Verification Engineer! In this position you will have the chance to ... and SOC). What you'll be doing: + Design and maintain the Full Chip Verification environment. + Understand the architecture specifications and develop the test… more
- Cisco (San Jose, CA)
- …and verification processes, debugging, methodology, and tools. * Experience in verifying blocks/clusters/ full chip level for ASIC . Preferred: * Post-silicon ... Who You'll Work With You will work with outstanding talent and vast ASIC development expertise in design, DV, DFT, physical design, and post-silicon validation The… more
- SpaceX (Irvine, CA)
- …will expand the performance and capabilities of the Starlink network. RESPONSIBILITIES: + Full chip and block level timing signoff and convergence through timing ... Sr. SOC/ ASIC Timing Signoff & Front-End Implementation Engineer (Silicon...post routed database for various timing signoff checks + Full chip and block level front-end implementation… more
- Cisco (San Jose, CA)
- …Verilog RTL to meet timing, performance, and power requirements. * Contribute to full chip integration and timing methodology/analysis. * Develop and analyze ... Cisco's silicon team provides an outstanding, unique experience for ASIC engineers by combining the resources offered by a...breadth of growth opportunities that working in a smaller ASIC team can provide. Your Impact * Write micro-architecture… more
- NVIDIA (Westford, MA)
- …work, to amplify human inventiveness and intelligence. NVIDIA is looking for best-in-class Senior ASIC Timing Design Engineers to join our outstanding Networking ... and low-power DPUs and SoCs at block level, cluster level, and/or full chip level. + Analyze and optimize design constraints and synthesis parameters to… more
- NVIDIA (Santa Clara, CA)
- …and closure of Nvidia's GPUs, CPUs, DPUs and SoCs at block level, cluster level, and/or full chip level. + Work with PD, DFX, Clocks, and other teams in coming ... and intelligence. We are now looking for a motivated ASIC Timing Engineer to join our dynamic and growing...experience in Timing and STA + Hands-on experience in full - chip /sub- chip Static Timing Analysis (STA)… more
- Cisco (San Jose, CA)
- …* End-to-end verification of one or more design blocks simultaneously while helping the full chip team with integration and support. * Test plan generation, ... in the world. You will engage in dynamic collaboration with Senior micro-architects, designers, and verification engineers and interact with cross-functional… more
- Amazon (Austin, TX)
- …Develop and maintain comprehensive gate-level simulation test plans for verifying ASIC functionality and timing. Analyze simulation results, identify and debug logic ... of Project Kuiper's sub-team responsible for defining and implementing the digital chip SOCs for communications via Low Earth Orbit satellites and Amazon gateways.… more
- Amazon (Austin, TX)
- …resources here to help you develop into a better-rounded professional. Custom SoCs (System on Chip ) live at the heart of AWS Machine Learning servers. As a member of ... rapid integration of emergent technologies. We're looking for an ASIC Design Eengineer to help us trail-blaze new technologies...Curious" mindset About the team Custom SoCs (System on Chip ) live at the heart of AWS Machine Learning… more
- Amazon (San Diego, CA)
- …applying sound business judgement combined with technical acumen. * Analyze Silicon Chip industry package and ATE trends and emerging technologies to identify ... solve IP ownership, capability and operational barriers. * Drive ASIC package, ATE, Qualification/FA Engineering/Consulting Services supplier strategies and… more
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