- Cisco (San Jose, CA)
- Senior ASIC Design Engineer Apply (https://jobs.cisco.com/jobs/Login?projectId=1431806) + Location:San Jose, California, US + Area of InterestEngineer - Hardware ... Verilog RTL to meet timing, performance, and power requirements. + Contribute to full chip integration and timing methodology/analysis. + Develop and analyze… more
- Draper (Boston, MA)
- Job Description Summary: We are seeking a Senior Analog/Mixed Signal ASIC Design Engineer to join our team in the Silicon Architecture group. Members of our ... most efficient design solution. We are involved in the full design lifecycle and often take chip -lead...or 0-2 years of experience with a PhD in ASIC Hardware Engineering or related. Additional Job Description: Additional… more
- NVIDIA (Westford, MA)
- …work, to amplify human inventiveness and intelligence. NVIDIA is looking for best-in-class Senior ASIC Timing Design Engineers to join our outstanding Networking ... and low-power DPUs and SoCs at block level, cluster level, and/or full chip level. + Analyze and optimize design constraints and synthesis parameters to… more
- NVIDIA (Santa Clara, CA)
- …of Nvidia's GPUs, CPUs, DPUs and SoCs at block level, cluster level, and/or full chip level. + Help in driving frontend and backend implementation including ... and intelligence. We are now looking for a motivated ASIC Timing Engineer to join our dynamic and growing...experience in Synthesis and Timing + Hands-on experience in full - chip /sub- chip Static Timing Analysis (STA),… more
- NVIDIA (Santa Clara, CA)
- …and closure of Nvidia's GPUs, CPUs, DPUs and SoCs at block level, cluster level, and/or full chip level. + Work with PD, DFX, Clocks, and other teams in coming ... and intelligence. We are now looking for a motivated ASIC Timing Engineer to join our dynamic and growing...experience in Timing and STA + Hands-on experience in full - chip /sub- chip Static Timing Analysis (STA)… more
- NVIDIA (Santa Clara, CA)
- …design tradeoffs and methodology on next generation CMOS technology. We are looking for a Senior ASIC Timing Engineer to join our dynamic and growing team! If ... experience. + 8+ years experience in Physical design/Timing. + Experience in full - chip /sub- chip Static Timing Analysis (STA), timing constraints generation… more
- NVIDIA (Santa Clara, CA)
- We are now looking for a Senior ASIC Design Engineer - DFX! NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 sparked ... Create and execute test plans to support both functional and DFT full - chip verification. + Support post-silicon bring-up and validation efforts including debug… more
- Tarana Wireless (Milpitas, CA)
- …that you will make such an impact on our products. We are looking for a Senior ASIC Verification Engineer that is self driven however knows when to collaborate ... to define verification strategies and execute plans at system or full chip level + Build and continuously improve verification infrastructure and methodologies… more
- Amazon (Austin, TX)
- …Develop and maintain comprehensive gate-level simulation test plans for verifying ASIC functionality and timing. Analyze simulation results, identify and debug logic ... of Project Kuiper's sub-team responsible for defining and implementing the digital chip SOCs for communications via Low Earth Orbit satellites and Amazon gateways.… more
- Amazon (Cupertino, CA)
- …resources here to help you develop into a better-rounded professional. Custom SoCs (System on Chip ) live at the heart of AWS Machine Learning servers. As a member of ... rapid integration of emergent technologies. We're looking for an ASIC Design Eengineer to help us trail-blaze new technologies...Curious" mindset About the team Custom SoCs (System on Chip ) live at the heart of AWS Machine Learning… more