- TSMC (San Jose, CA)
- …responsible for the physical design implementation PnR run, Performance/ Power /Area ( PPA ) comparison, congestion & DRC analysis , and design optimization. You ... Senior Physical Design Engineer (7051) - TSMC Join...and design optimization. Evaluate flow and methodologies to optimize power , performance, and area ( PPA ). Analyze standard… more
- TSMC - Taiwan Semiconductor Manufacturing Company Limited (San Jose, CA)
- …responsible for the physical design implementation PnR run, Performance/ Power /Area ( PPA ) comparison, congestion & DRC analysis , and design optimization. You ... may also do synthesis, debugging & data analysis , scripting, STA or timing analysis . You...and design optimization. Evaluate flow and methodologies to optimize power , performance, and area ( PPA ). Analyze standard… more
- AMD (San Jose, CA)
- …ensure cohesive system-level design. Specify architecture requirements, conduct early-stage analysis , and create detailed specifications. Drive PPA optimization ... advance your career. THE ROLE We are seeking a Senior Member of Technical Staff (SMTS) SoC Architect to...strong analytical skills, and the ability to balance performance, power , and area trade-offs. You communicate effectively across teams… more
- Flux Computing (San Francisco, CA)
- …including synthesis, static‑timing closure, formal and constrained‑random verification. Analyse power , performance and area ( PPA ); implement innovative ... Join to apply for the Senior / Staff Digital Design Engineer role at...Expertise with industry‑standard EDA flows: RTL synthesis, CDC/RDC, STA, power ‑intent (UPF/CPF), lint, and gate‑level simulation. Demonstrated FPGA prototyping… more
- Advanced Micro Devices (San Jose, CA)
- …optimize SoC control bus protocols, reset flows, clocking strategies, and power domains. Drive early‑stage architectural analysis , modeling, and specification ... system‑level mindset to solving architectural challenges. You are passionate about performance, power , and scalability, and have a strong grasp of silicon design… more
- AMD (San Jose, CA)
- …optimize SoC control bus protocols, reset flows, clocking strategies, and power domains. Drive early‑stage architectural analysis , modeling, and specification ... create something extraordinary. Key Responsibilities Drive architecture of key IPs including their PPA tradeoffs, Interconnect, and integration into SoC Define and… more
- Efficient Computer (San Francisco, CA)
- …of computing, we would like to talk to you. Efficient is hiring a senior ASIC Physical Design Engineer with experience in backend implementation from Netlist to ... GDSII. We seek individuals to leverage low‑ power techniques and design-technology co‑optimization in advanced technology nodes...planning, place and route, clock tree synthesis, static timing analysis , ERC, IR drop analysis , electromagnetic … more
- NVIDIA (Santa Clara, CA)
- …design methodologies for implementation of GPU, CPU and SOCs, with emphasis on PPA ( Power , Performance, Area) and runtime improvement of the physical design ... power and area optimization, timing, IR and EM analysis and closure + Work with internal and external...in Physical Design Engineering + Proven track record of PPA improvement on high performance and low power… more
- ThermoFisher Scientific (Carlsbad, CA)
- …(Mon-Fri) **Environmental Conditions** Office **Job Description** **Role Summary** The Finance Senior Manager for the Pharma Analytics Business Unit is the primary ... for the Pharma Analytics business, serving global biopharma customers. The senior manager will drive financial rigor, elevate performance insights, and strengthen… more
- Google (Sunnyvale, CA)
- …with internal logic and internal and external teams to achieve the best Power /Performance Analysis ( PPA ). This includes conducting feasibility studies for ... Senior ASIC Physical Design Engineer _corporate_fare_ Google _place_...including Scan, MBIST and LBIST. + Understanding of performance, power and area ( PPA ) trade-offs. **About the… more
