- Celestial AI (Santa Clara, CA)
- …, physical synthesis and ECO implementation as needed. Lead design methodology improvements, driving efficiency in RTL -to-GDSII flows. Drive post-silicon ... assembly, and packaging suppliers. ABOUT THE ROLE We are looking for a Senior ASIC/VLSI Synthesis and Design Engineer to drive the development of high-performance,… more
- Qualcomm (Austin, TX)
- … Analysis and Estimation Analyzing performance and power on use cases RTL and Synthesis based Power Optimization Thermal Analysis and Optimization Performance ... responsible for all aspects of power estimation/implementation/verification/minimization and associated methodology /flow development. The focus will be on delivering best… more
- NVIDIA (Santa Clara, CA)
- …What you'll be doing: + You will be part of NVIDIA's RTL analysis CAD team, responsible for developing flows, methodology , and application support for Clock ... part of a diverse team creating NVIDIA's chip design methodology ! We're responsible for the RTL CDC...deploy, and support state-of-the-art EDA tools and methodologies for RTL analysis . + Serve as an in-house… more
- Cisco (San Jose, CA)
- Senior DFx/ RTL Engineer Apply (https://jobs.cisco.com/jobs/Login?projectId=1447271) + Location:San Jose, California, US + Area of InterestEngineer - Hardware + ... functional verification **Preferred Qualification:** + DFT CAD development - Test Architecture, Methodology and Infrastructure + Test Static Timing Analysis +… more
- NVIDIA (Santa Clara, CA)
- …to amplify human inventiveness and intelligence. We are seeking an innovative senior timing signoff and constraint methodology engineer to develop pioneering ... develop methodology and flows to validate timing constraints from RTL to netlist via structural, functional and cross-hierarchy constraints checks. We're looking… more
- NVIDIA (Santa Clara, CA)
- …field (or equivalent experience). + 6+ years of experience in static timing analysis , methodology , or constraint development. + Strong expertise in asynchronous ... human inventiveness and intelligence. We are seeking a highly skilled Timing Methodology Engineer with expertise in asynchronous timing and I/O interface modeling to… more
- NVIDIA (Santa Clara, CA)
- …now looking for a Senior Design for Debug (DFD) Architect and Methodology Engineer! NVIDIA is seeking a DFD Architect to implement hardware and software ... tools. + Great understanding of ASIC design flow including RTL design, verification, logic synthesis, timing analysis ...including RTL design, verification, logic synthesis, timing analysis and bringup. + Strong interpersonal skills and an… more
- Microsoft Corporation (Redmond, WA)
- …designers and software engineers around the world. We are looking for a ** Senior Quantum Engineer - Cryo-CMOS Digital Circuit Design** . Our Cryo-CMOS team is ... + Be responsible for + Logic design/Register Transfer Level ( RTL ) entry + RTL to GDS implementation...and room temperature measurements of the ASICs and perform analysis and reporting of the measurement results. + Use… more
- Northrop Grumman (Linthicum Heights, MD)
- …UVM + Experience developing testplans, participating in reviews, test development and RTL debug ** Senior Principal Engineer Basic Qualifications:** + Bachelor's ... for you to join our team as a Principal Digital Verification Engineer/ Senior Principal Digital Verification Engineer based out of Linthicum, MD or Morrisville,… more
- NVIDIA (Santa Clara, CA)
- …In-silicon measurement, Reset and Boot controllers. + You will be responsible for the RTL design, logic synthesis, and timing analysis of several modules. + ... We are now looking for a Senior ASIC Design Engineer to join our System...design concepts and experience in ASIC design flow including RTL design, verification, logic synthesis and timing analysis… more
