• Senior Verification Engineer

    Microsoft Corporation (Mountain View, CA)
    …will manage and optimize the Cloud infrastructure. We are looking for a ** Senior Verification Engineer** to join our team! **Responsibilities** + Perform ... paramount importance. To achieve this goal, the Artificial Intelligence System on Chip (AISoC) team is instrumental in defining...pre-silicon verification for complex IP , including creating testplans,… more
    Microsoft Corporation (01/10/26)
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  • Senior Verification engineer

    Two95 International Inc. (Sunnyvale, CA)
    Hi, Title: Lead / Senior Verification engineer Location: San Jose, CA / Santa Clara, CA Duration: 6+ Months Rate: $Open Skills: UVM and System Verilog ... * 5+ or more years of proven experience on ASIC / SoC / IP Verification . * Strong experience in SystemVerilog and UVM verification methodologies *… more
    Two95 International Inc. (12/08/25)
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  • Senior IP Verification

    NVIDIA (Santa Clara, CA)
    … architects and other verification engineers to formalize product features + Verify IP 's using System Verilog and UVM + Build testbenches and enhance flows ... We are now looking for a Senior Verification Engineer! NVIDIA has been... verification experience + Expertise in verifying sophisticated IP 's with System Verilog + Experience with… more
    NVIDIA (01/10/26)
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  • Senior Design Verification Engineer

    Microsoft Corporation (Mountain View, CA)
    …features. + Lead a pre-silicon verification team for the development of custom Intellectual Property ( IP ) and Subsystem (SS) components with focus on ... to Microsoft cloud hardware. We are looking for a Senior Design Verification Engineer for customer focused...of the following: interconnect fabrics, Network on Chip(NOCs), AXI-4 protocol base other complex IP /blocks or subsystems.… more
    Microsoft Corporation (01/09/26)
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  • Principal Digital Verification Engineer/…

    Northrop Grumman (Linthicum Heights, MD)
    Verification Methodology) and SystemVerilogl. + Development of testbench, tests, verification IP (VIP), verification models, coverage models, extensive ... you to join our team as a Principal Digital Verification Engineer/ Senior Principal Digital Verification ...object oriented programming languages and concepts + Experience with Verification IP integration and/or development + Experience… more
    Northrop Grumman (01/02/26)
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  • Senior Principal Design Verification

    BAE Systems (Largo, FL)
    …your leadership skills while leading small to medium sized DV teams + Create reusable Verification IP to be shared across the organization; + Drive changes to ... and advancing your career. BAE is looking for experienced senior level FPGA Design Verification Engineers who...VHDL + FPGA Design Experience + Experience creating reusable Verification IP . + Experience leading small to… more
    BAE Systems (01/10/26)
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  • Senior Principal FPGA Verification

    BAE Systems (Westminster, CO)
    …on a variety of R&D, proof of concept, and production programs. + Verification for space systems , high reliability electronic systems . Assignments ... US Secretary of Education, US Department of Education. + Verification experience with to include partitioned digital systems...desired. + Solid electronic systems or embedded systems background. + Experience with VHDL/Verilog and System more
    BAE Systems (12/23/25)
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  • Senior Engineer - ASIC/FPGA…

    BAE Systems (Cedar Rapids, IA)
    …your leadership skills while leading small to medium sized DV teams; + Create reusable Verification IP to be shared across the organization; + Drive changes to ... their precision navigation missions. BAE is looking for experienced senior level ASIC/FPGA Design Verification Engineers who...VHDL + FPGA Design Experience + Experience creating reusable Verification IP . + Experience leading small to… more
    BAE Systems (12/24/25)
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  • Senior ASIC Verification Engineer

    NVIDIA (Austin, TX)
    …passion for verification methodologies and implementation that enable high quality system -level IP design and robust verification at multiple environment ... high-level and broad impact at NVIDIA working on a system -level IP responsible for measuring performance on...you'll be doing: + Design and maintain the unit level/sub- system Verification environment. + Understand the architecture… more
    NVIDIA (12/18/25)
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  • Senior Modem Design Verification

    Amazon (San Diego, CA)
    …Work with the design and communication systems team and participate in system level verification using test benches constructed using UVM, SystemC and DPI-C ... you will: . Implement a state of the art verification environment for modem IP and subsystem...systems - Familiarity with Matlab - Modem design verification experience - System C or Matlab… more
    Amazon (12/09/25)
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