- NVIDIA (Santa Clara, CA)
- …Methodology organization is driving the next generation of AI-assisted timing and constraint sign-off, integrating advanced analytics, orchestration frameworks, and ... closure across multi-billion transistor chips. We are seeking an Applied AI Engineer to lead end-to-end solution development - spanning data generation, model… more
- Google (Mountain View, CA)
- Senior Silicon CAD Engineer ...Silicon SoC projects (eg, RTL generation, design verification, AI-enabled CAD , design QA, timing , and low power). ... 5 years of industry experience in VLSI design or CAD flow development. + Experience with front-end design tools...10 years of experience in software development or front-end CAD . + Experience with ML algorithms and AI application… more
- NVIDIA (Santa Clara, CA)
- …work, to amplify human inventiveness and intelligence. We are seeking an innovative Senior Timing Methodology Engineer to help drive sign-off strategies ... flow, and tool for high-speed designs, with focus on CAD and automation. + Develop custom flows for validating...+ Collaborate with technology leads, VLSI physical design, and timing engineers to define and deploy the most sophisticated… more
- NVIDIA (Santa Clara, CA)
- …lasting impact on the world! We are currently looking for a Senior Methodology Engineer to develop and support our CAD tooling in our Circuit Solutions Group ... or equivalent experience + 6+ years of experience in VLSI CAD flows and methodology + Timing closure and STA tool experience required + Good programming skills… more
- SpaceX (Sunnyvale, CA)
- Sr. SOC/ASIC Physical Design Methodology/ CAD Engineer (Silicon Engineering) Sunnyvale, CA Apply SpaceX was founded under the belief that a future where humanity ... goal of enabling human life on Mars. SR. SOC/ASIC PHYSICAL DESIGN METHODOLOGY/ CAD ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our experience… more
- Honeywell (Phoenix, AZ)
- You will report directly to the Senior Engineering Manager and you'll work at our Plymouth, MN location on a Hybrid work schedule. (Other allowed Honeywell Aerospace ... IC Design engineers to craft and maintain optimized EDA CAD flows for a highly heterogeneous set of IC...S-EDA OPC jobs, Cadence Spectre SPICE simulations, Synopsys-based static timing analyses). + Construct application slurm flows to maximize… more
- Northrop Grumman (Jessup, MD)
- …new advantages to the warfighter. We are seeking a front-end ASIC design engineer for design and verification of full-custom digital circuits. Must be proficient in ... plans. Must be knowledgeable in synthesis, SDC constraints, formal verification, and static timing . Knowledge of scan insertion and ATPG is a plus. Able to interface… more
- ManpowerGroup (Germantown, WI)
- …growing company in Germantown, WI on a highly visible and direct hire/permanent Senior Tooling Engineer & Technical Leader position that has strong advancement ... is available.** **JOB DESCRIPTION** The company is seeking a Senior Tooling Engineer & Technical Leader with...die design expertise. + Do more than sit behind CAD all day. + Solve complex tooling and manufacturability… more
- Cisco (Maynard, MA)
- …working in a smaller ASIC team can provide. Your Impact As a Physical Design Engineer , you will play a key role in the full RTL-to-GDSII implementation flow for ... advanced semiconductor nodes. You will optimize floor planning and timing , analyze and improve backend design flows, and collaborate across teams to ensure the… more
- Microsoft Corporation (Mountain View, CA)
- …engineers so that they can deliver cutting-edge silicon solutions for Microsoft. As a Senior Front-End CAD Engineer , you'll drive the development and ... with design teams across Microsoft Silicon to deliver scalable, high-performance CAD solutions. #azurehwjobs #SCHIE **Responsibilities** - Be part of a central… more