- NVIDIA (Santa Clara, CA)
- …work, to amplify human inventiveness and intelligence. We are seeking an innovative senior timing signoff and constraint methodology engineer to develop ... this role, you'll develop methodology and flows to validate timing constraints from RTL to netlist via structural, functional and cross-hierarchy … more
- NVIDIA (Santa Clara, CA)
- …work, to amplify human inventiveness and intelligence. We are seeking a highly skilled Timing Methodology Engineer with expertise in asynchronous timing and ... You will play a critical role in defining cross-domain timing constraints , validating IO timing ...equivalent experience). + 6+ years of experience in static timing analysis, methodology , or constraint development. +… more
- NVIDIA (Santa Clara, CA)
- …work, to amplify human inventiveness and intelligence. We are seeking an innovative Senior Timing Methodology Engineer to help drive sign-off strategies ... can offer. + Work on various aspects of STA, constraints , timing and power optimization. What We...sign-off + Good knowledge of extraction, device physics, STA methodology and EDA tools limitations. Good understanding of mathematics/physics… more
- NVIDIA (Santa Clara, CA)
- …chip level. + Work with PD, DFX, Clocks, and other teams in coming up with timing closure strategy, creating timing constraints , driving timing and power ... ECO implementation + Apply knowledge and experience to improve timing convergence flows working with the methodology ...in full-chip/sub-chip Static Timing Analysis (STA) and timing convergence, timing constraints generation… more
- NVIDIA (Santa Clara, CA)
- …and convergence of high-performance designs. + You will be responsible for all aspects of timing including setting up timing constraints , timing analysis ... timing closure of high-speed designs. + Strong background and experience in timing constraints generation, clocking, process variations and signal integrity +… more
- SpaceX (Irvine, CA)
- …signoff checks + Full chip and block level front-end implementation from timing constraints development, synthesis, formal verification, power intent generation ... & validation + Develop block and full chip level timing constraints for test modes + ...Functional ECOs for complex blocks + Deploy and enhance methodology and flows related to timing constraint… more
- Cisco (San Jose, CA)
- …, performance, and power requirements. * Contribute to full chip integration and timing methodology /analysis. * Develop and analyze functional coverage. * Help ... define, evolve, and support our design methodology . * Collaborate with the verification team to address...or System Verilog programming skills * Experience with simulators/synthesis/static timing constraints and related tools (eg, VCS,… more
- Ford Motor Company (Dearborn, MI)
- …workforce and time calculation. + Responsible for defining and managing the technical, timing and budget of multiple projects + Document and track enablers and ... teams to successfully complete projects within time & resource constraints + Track project progress & report effectively on...blockers & changes to customer as well as internal senior management + Track project costs & drive cost… more
- Polaris Industries (Medina, MN)
- …- Adobe Creative Suite. . Ability to deliver successful designs under tight timing constraints and provide examples of such scenarios throughout career. **The ... empower us to THINK OUTSIDE.** **Job Summary:** As a Senior CMF Designer at Polaris Design, you will contribute...OEM space. . Knowledge of the design process and methodology , as well as the CMF development process. .… more