- Draper (Boston, MA)
- …Description Summary: Draper's Digital Design Team is seeking a motivated and experienced Senior UVM Digital Verification Engineer to tackle novel ... and ASICs. In this role, you will apply modern verification strategies to complex digital and mixed-signal... digital and embedded hardware platforms. + Develop verification and test plans + Develop UVM … more
- US Tech Solutions (Goleta, CA)
- … verification prior to tape-out. **Responsibilities:** + Perform pre-silicon functional verification of digital designs using UVM and SystemVerilog ... of high-performance SoCs and related subsystems. + This role requires a senior -level verification engineer who can work independently and take ownership of… more
- Northrop Grumman (Linthicum Heights, MD)
- …of your career. We are looking for you to join our team as a Principal Digital Verification Engineer/ Senior Principal Digital Verification Engineer ... NC. This requisition may be filled as a Principal Digital Verification Engineer or a Senior...complex ASIC at block level and SOC level using UVM (Universal Verification Methodology) and SystemVerilogl. +… more
- Huntington Ingalls Industries (Fort Meade, MD)
- …Engineering, Computer Science, or a related field * Experience with modern digital verification and modeling languages: SystemVerilog, SystemC, C/C++, Matlab, ... short video: https://vimeo.com/732533072 Job Description Do you enjoy challenging digital design verification problems? HII Mission Technologies...etc. * UVM concepts * Directed, constrained-random, and assertion-based … more
- Northrop Grumman (Jessup, MD)
- …**a Top Secret/SCI security clearance with Polygraph** **.** **Basic Qualifications Senior Principal Digital Verification Engineer:** + Bachelor's ... Secret/SCI security clearance with Polygraph** **.** **Preferred Qualifications Principal / Senior Principal Digital Verification Engineer:** + Advanced… more
- Broadcom (San Jose, CA)
- …Account, please Sign-In before you apply.** **Job Description:** Broadcom is looking for a senior level Digital Design Verification engineer. In this highly ... PhD in Electrical Engineering or Computer Engineering with 10+ years of experience in digital design verification + Hands on experience in SV UVM , SV RNM and… more
- BAE Systems (Westminster, CO)
- …scripting languages (eg Ruby, Python, TCL). + Experience in documentation and verification of high-speed digital electronics, FPGAs, and embedded processor ... Other incentives may be available based on position level and/or job specifics. ** Senior Principal FPGA Verification Engineer - $15K Sign On Bonus** **115210BR**… more
- Capgemini (Seattle, WA)
- …flows. **Preferred Qualifications** + Experience verifying GPU/CPU designs and developing UVM -based verification environments from scratch. + Background in ... **Job Description:** We are seeking a SoC Design Verification Engineer to join our team 100% onsite...to 10 years of hands-on experience with SystemVerilog and UVM methodology. + Proficiency in one or more of… more
- BAE Systems (Nashua, NH)
- …growing your skills, and advancing your career. BAE is looking for experienced senior level FPGA Design Verification Engineers who can plan, architect, and ... Other incentives may be available based on position level and/or job specifics. ** Senior Principal Design Verification Engineer - FPGA - (Sign-on Bonus)**… more
- BAE Systems (Cedar Rapids, IA)
- …to execute their precision navigation missions. BAE is looking for experienced senior level ASIC/FPGA Design Verification Engineers who can plan, architect, ... incentives may be available based on position level and/or job specifics. ** Senior Principal Engineer - ASIC/FPGA Verification (Hybrid)** **117726BR** EEO Career… more