- NVIDIA (Santa Clara, CA)
- …to amplify human inventiveness and intelligence. We are seeking an innovative Timing Methodology Engineer to help drive multi-physics sign-off strategies for the ... a "learning machine" that constantly evolves by adapting to new opportunities that are hard to resolve, that only...for sign-off. + Knowledge of extraction, device physics, STA methodology and EDA tools limitations. + Shown understanding of… more
- NVIDIA (Santa Clara, CA)
- …amplify human inventiveness and intelligence. We are seeking a highly skilled Timing Methodology Engineer with expertise in asynchronous timing and I/O interface ... a "learning machine" that constantly evolves by adapting to new opportunities that are hard to resolve, that only...modeling to architect and deploy robust timing signoff practices across high-performance SoCs. You will play a… more
- Amazon (Cupertino, CA)
- …emergent technologies. We're looking for an ASIC Physical Design Methodology Engineer to help us trail-blaze new technologies and architectures, while ... TAT improvements Work with EDA tool vendors to evaluate new methods, resolve bugs, improve usability. Fine tune cloud...7yrs in EE/CS - 5+ years developing physical design methodology or CAD flows in synthesis, PNR, and sign-off… more
- Amazon (Austin, TX)
- …AI services for our customers' businesses. We are seeking experienced Physical Design Engineer to build the next generation of our cloud server platforms. Our ... low cost. You'll provide leadership in the application of new technologies to large scale deployments in a continuous...- You will create and support innovative physical design methodology and CAD flows. - Develop cloud infrastructure to… more
- NVIDIA (Santa Clara, CA)
- …the world! We are currently looking for a Sr VLSI Physical Verification Methodology Engineer . What you'll be doing: + Developing physical verification ... processors and SOCs. + Participate in developing physical verification flows for new technologies - DRC, LVS, Antenna flows - improving automation and expert… more
- Microsoft Corporation (Austin, TX)
- …to Silicon, including writing test plans, developing tests, debugging failures and coverage signoff in C/C++ and Universal Verification Methodology (UVM) + 3+ ... mission. As Microsoft's cloud business continues to grow the ability to deploy new offerings and hardware infrastructure on time, in high volume with high quality… more
- Cadence Design Systems, Inc. (San Jose, CA)
- …make an impact on the world of technology. Job Title: Sr Application Engineer (f/m/d) Location: Stockholm (Kista), Sweden Reports to: AE Group Director Job Overview: ... The Cadence Application Engineer (AE) role is a great opportunity to employ...and product development teams supporting Cadence's Custom IC and Signoff software products including: + Virtuoso Schematic Editor +… more
- NVIDIA (Santa Clara, CA)
- …impact on the world! We are currently looking for a Sr VLSI Physical Verification Methodology Engineer . What you'll be doing: + Responsible for support and debug ... methodologies to improve workflow efficiency and timely issue detection. Integrate new workflows and checks into larger workflow automation systems. + Participate… more
- Cadence Design Systems, Inc. (Irvine, CA)
- …signoff ) and/or experience with functional and formal verification tools/ methodology , VIP. Understanding of semiconductor manufacturing eco-systems. * Deep ... required. * Min. 7 years in sales and account management or as a Applications Engineer or Design Engineer with proven track record of success * Deep… more
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