• Signoff Static Timing…

    Qualcomm (San Diego, CA)
    …for the Snapdragon chips powering billions of mobile devices. The position requires Signoff Timing and spice simulation experience, with CAD development skills ... of STA features and Timing concepts. + 2-6 years of experience in Signoff Timing of SoCs at either top-level or block-level. * 2-6 years of experience with… more
    Qualcomm (06/03/25)
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  • Implementation Timing / STA Design Engineer

    Qualcomm (Santa Clara, CA)
    …for various modes/corners and low-power multi-voltage domain crossings, and signoff with static timing analysis . + Collaborate closely with RTL design ... Team is looking for skilled engineers to focus on timing constraints development, power analysis , STA, and timing closure for premium-tier chips.… more
    Qualcomm (07/08/25)
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  • Static Timing Analysis…

    Google (Mountain View, CA)
    …. + Be responsible for delivering System-on-Chip (SoC) Static Timing Analysis . + Define SoC timing signoff process corners, derates, uncertainties ... + Experience with ASIC design flows and methodology of static timing analysis . + Experience...full chip timing constraint creation and validation, timing signoff checklist criteria, perform full chip… more
    Google (06/21/25)
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  • SOC/ASIC Physical Design Engineer (Silicon…

    SpaceX (Sunnyvale, CA)
    …drive execution + Run, debug, and fix signoff closure issues in static timing analysis (STA), noise, logic equivalency, physical verification, ... (eg synthesis, floorplanning, power/ground grid generation, place and route, timing , noise, physical verification, electromigration, voltage drop, logic equivalency… more
    SpaceX (06/20/25)
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  • Sr. SOC/ASIC Physical Design Engineer (Silicon…

    SpaceX (Bastrop, TX)
    …drive execution + Run, debug, and fix signoff closure issues in static timing analysis (STA), noise, logic equivalency, physical verification, ... (eg synthesis, floorplanning, power/ground grid generation, place and route, timing , noise, physical verification, electromigration, voltage drop, logic equivalency… more
    SpaceX (06/19/25)
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  • ASIC Implementation Engineer - Static…

    Meta (Sunnyvale, CA)
    …our Infrastructure organization. **Required Skills:** ASIC Implementation Engineer - Static Verification Responsibilities: 1. Perform Flat and Hierarchical Clock ... work with the Designers to create waivers 4. Perform RTL Design for Testability Analysis and improve the Design for Testability coverage for Stuck-at faults 5. Run… more
    Meta (06/25/25)
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  • ASIC Engineer, Methodology

    Meta (Sunnyvale, CA)
    …equivalent practical experience 10. 12+ years of experience in: STA ( Static Timing Analysis ), Modeling, Signoff methodology development and flows, and ... Area (PPA), and design integrity for Meta SOCs 2. Develop timing signoff flow/methodology, automation for large complex disaggregated ASICs and test structures… more
    Meta (06/25/25)
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  • Senior Async and IO Timing Methodology…

    NVIDIA (Santa Clara, CA)
    …Engineering or related field (or equivalent experience). + 6+ years of experience in static timing analysis , methodology, or constraint development. + Strong ... and I/O interface modeling to architect and deploy robust timing signoff practices across high-performance SoCs. You... analysis . + Own and evolve I/O interface timing signoff , including external interface modeling (eg,… more
    NVIDIA (05/22/25)
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  • STA/Emir IC Solutions Architect

    Cadence Design Systems, Inc. (Austin, TX)
    … analysis , place and route, extraction, spice etc. Job Responsibilities: + Perform Static timing analysis , glitch, noise analysis , extraction using ... Tempus - Signoff tool. Execute and deliver on timing analysis , ECO flows, Extraction, Power, EMIR...VLSI, Semiconductor, Electrical or Computer Engineering. + Expert in Static Timing Analysis with knowledge… more
    Cadence Design Systems, Inc. (07/09/25)
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  • STA Principal Application Engineer

    Cadence Design Systems, Inc. (Austin, TX)
    …innovators who want to make an impact on the world of technology. Responsibilities; Perform Static timing analysis , glitch, noise analysis using Tempus ... and customer sites. Requirements; 10+ years of experience in Static timing analysis , Individual should...Tempus - Signoff tool. Execute and deliver on timing analysis & ECO flows and ensure… more
    Cadence Design Systems, Inc. (07/02/25)
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