- Apple Inc. (Cupertino, CA)
- SoC DRAM Memory Subsystem Validation Engineering Program Manager Cupertino, California, United States Hardware Come and join the team that crafts Apple's ... the next big thing that will surprise and delight the world! Description The SoC DRAM Memory Subsystem Validation and Debug Program Manager will drive… more
- Apple Inc. (Santa Clara, CA)
- …crafting special purpose cache and controller which is part and parcel of the SOC memory hierarchy. Responsibilities Design and develop hardware for cache ... the cache subsystem . Minimum Qualifications In-depth knowledge of memory subsystem Academic experience with RTL/micro-architecture development Good… more
- NVIDIA (Santa Clara, CA)
- …and comprehensive validation. + Architecture Review: Analyze DRAM datasheets, Memory Subsystem Architecture, and SoC architecture specifications to ... in groundbreaking developments in Artificial Intelligence, High-Performance Computing and Visualization. NVIDIA's SoC Memory Subsystem team is looking for… more
- NVIDIA (Santa Clara, CA)
- …and comprehensive validation. + Architecture Review: Analyze DRAM datasheets, Memory Subsystem Architecture, and SoC architecture specifications to ... Tuning: Tune the DRAM interface and manage the memory subsystem configuration, including enhancements to initialization, functionality, performance… more
- NVIDIA (Santa Clara, CA)
- NVIDIA is now looking for a Senior Memory System Engineer to join our ASIC Memory Subsystem team! As a Senior Systems Engineer at NVIDIA, you'll join a group ... to determine optimum performance, power, function and RAS in memory for Next generation SOC and Systems....memory evaluation / validation and failure issues on memory technology. + Collaborate with DRAM suppliers… more
- Micron Technology, Inc. (Boise, ID)
- …solutions. + Drive pathfinding initiatives for system architectures incorporating LPDDR and DRAM memory technologies. + Explore memory features that ... + Exposure to JEDEC standards and specification-setting processes. + Understanding of memory subsystem operation in high-performance computing and AI frameworks.… more
