- Cognichip (Redwood City, CA)
- …possible at the nexus of silicon design and machine learning. As a Staff Chip Design Engineer on our team, you'll tackle real-world scientific and ... the processes for dataset collection, curation, and enhancement. You'll fuse knowledge of chip design and ML into end-to-end silicon design flows. If you… more
- Microchip (San Jose, CA)
- Senior Technical Staff Engineer - Design for Test Company Description Are you looking for a unique opportunity to be a part of something great? Want to join ... timing closure, power analysis during test and quantifying full chip test coverage. Establish and maintain DFT design... chip test coverage. Establish and maintain DFT design and insertion guidelines and documents best practices for… more
- SQL Pager LLC (San Francisco, CA)
- Principal/Senior Staff / Staff ASIC Design Engineer (RISC-V) Client Overview Client is building the first latency optimized SoC for their industry. Using ... ( Staff ) of general experience as a CPU Design Engineer for building complex SoCs. ◦...Programmable Interrupt Controller Debug and Trace Low Power Implementation. Chip Security Cryptography Nice to have Experience in working… more
- Advanced Micro Devices, Inc. (San Jose, CA)
- …where communication and teamwork are highly valued. Key Responsibilities As an ASIC Design Engineer , your responsibilities span various aspects of SOC design ... with other specialists that are members of the SOC Design - Verification, Emulation, STA, and Physical Design...Experience Hands on experience in all aspects of the chip development process with proficiency in front end tools… more
- Advanced Micro Devices (San Jose, CA)
- …beyond. Together, we advance your career. THE ROLE: We are looking for a self‑motivated senior design engineer to be part of a leading team to drive and improve ... As a key contributor, you will focus on RTL design and validation of high‑speed interfaces such as chip ‑to‑ chip interconnect, both on system and on package,… more
- AMD (San Jose, CA)
- …beyond. Together, we advance your career. The Role We are looking for a self‑motivated senior design engineer to be part of a leading team to drive and improve ... As a key contributor, you will focus on RTL design and validation of high‑speed interfaces such as chip ‑to‑ chip interconnect, both on system and on package,… more
- Samsung Semiconductor, Inc. (San Jose, CA)
- Position Title: Senior Staff Engineer , Serdes Layout Design...SkillCad and so on. Desire to have experience on chip level design , like bump, pad, and ... Do As a senior high speed mixed-signal layout/analog layout engineer , you will be working with circuit designers located...policy Working with remote circuit designers to determine the chip floorplan. You need to come up with strategies… more
- Samsung Semiconductor (San Jose, CA)
- Senior Staff Engineer , Serdes Layout Design ...Calibre LVS, DRC, SkillCad, and so on. Experience on chip level design , like bump, pad, and ESD ... Work policy. What You'll Do As a senior high‑speed mixed‑signal layout/analog layout engineer , you will be working with circuit designers located in San Jose, CA… more
- Conductor (San Jose, CA)
- …including Virtuoso, Calibre LVS, DRC, SkillCad, and similar. Have experience with chip ‑level design , eg, bump, pad, and ESD strategies. Communicate effectively ... Work policy. What You'll Do As a senior high‑speed mixed‑signal layout/analog engineer , you will work with circuit designers located in San Jose, California,… more
- Flux Computing (San Francisco, CA)
- Senior / Staff Analog Design Engineer - High Speed SerDes 4 days ago Be among the first 25 applicants The Role We are seeking an experienced Analog /RF IC ... central to realising Flux's multi‑terabit‑per‑second optical fabric. Responsibilities Define, design and verify SerDes cores operating at >25Gb/s‑per‑lane, including… more
