• Static Timing Engineer…

    Google (Sunnyvale, CA)
    …or a related field, or equivalent practical experience. + 2 years of experience in static timing analysis. + Experience in Primetime or Tempus Tcl scripting and ... static timing analysis debug and problem solving....understand and implement the requirements. The ML, Systems, & Cloud AI (MSCA) organization at Google designs, implements, and… more
    Google (07/02/25)
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  • Principal Design Engineer

    Microsoft Corporation (Mountain View, CA)
    …ability to contribute to diverse and inclusive teams. + Solid understanding of synthesis, static timing checks, DFT + Deep knowledge of front-end tools, clock ... Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is the...that mission. We are looking for a **Principal Design Engineer ** to work in the dynamic Microsoft Artificial Intelligence… more
    Microsoft Corporation (07/25/25)
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  • Principal Digital Engineer

    Renesas (Duluth, GA)
    …architecture, and verification reviews + Oversee digital backend design, including synthesis, static timing analysis, and logic equivalence checking + Create ... Principal Digital Engineer Job Description + Propose, architect, and design...and DFT insertion with high coverage + Experience with static timing analysis and creation of place… more
    Renesas (07/31/25)
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  • Senior Silicon Engineer

    Microsoft Corporation (Santa Clara, CA)
    …Domain Crossing design techniques. + Proficiency in Verilog, System Verilog, Synthesis and Static Timing Analysis. + Self-motivated and able to work effectively ... Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is the...Systems & Infrastructure group is seeking a Senior Silicon Engineer . You will join our front-end silicon team and… more
    Microsoft Corporation (07/30/25)
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  • SDC Engineer (eInfochips Inc)

    Arrow Electronics (San Jose, CA)
    …**block/full chip SDC development** in functional and test modes. + Experience in ** Static Timing Analysis** and prior working experience with STA tools like ... **Position:** SDC Engineer (eInfochips Inc) **Job Description:** **Position: SDC ...with physical design and DFT teams to close **fullchip timing ** in multiple timing modes. + Option… more
    Arrow Electronics (06/06/25)
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  • Physical Design Engineer

    Cisco (Maynard, MA)
    …Mentor + Experience with floor planning & partitioning, synthesis, place & route, static timing analysis (STA), formal equivalence check, Clock Tree Synthesis, ... Physical Design Engineer Apply (https://jobs.cisco.com/jobs/Login?projectId=1444081) + Location:Maynard, Massachusetts, US + Alternate LocationRemote + Area of… more
    Cisco (07/11/25)
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  • Sr. Principal EDA Software Engineer (C++,…

    Cadence Design Systems, Inc. (San Jose, CA)
    …a member of an expert R&D team creating technologies and products that enable static and dynamic transistor level analysis of the most advanced custom digital and ... EDA tools and one or more of transistor level timing , power, noise, aging, reliability, and emir analysis +...models + Experience with distributed programming, database design, and cloud APIs for distributed computing Your work will be… more
    Cadence Design Systems, Inc. (06/24/25)
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