- US Tech Solutions (Goleta, CA)
- …AXI, JTAG preferred + Experience in analog and real number modeling preferred **Skills:** + UVM / System Verilog + Design Verification + Ethernet, SPI, ... + The project relates to the design and verification of a custom controller for...simulations + Experience in ethernet and SPI required + UVM / System Verilog experience 5+ years… more
- Cisco (San Jose, CA)
- …combined with 5 years of related experience * Experience in System Verilog / UVM . * Experience with ASIC design and verification processes, debugging, ... with outstanding talent and vast ASIC development expertise in design , DV, DFT, physical design , and post-silicon...micro-architects, front-end designers, and verification engineers. Cisco is a system company, so you can also use the ASIC… more
- ManpowerGroup (Fort Collins, CO)
- …and debug test failures. Ideal candidate has extensive experience of IP level verification using UVM and System Verilog within the last 3 years. Knowledge of ... Remote **Summary:** Be part of a team working on design verification for complex IPs and sub- systems ...with the lead engineer; 60% of coding, specifically in System Verilog and UVM test… more
- Amazon (Sunnyvale, CA)
- …10+ years or more of practical semiconductor design verification experience including System Verilog , UVM , assertions and coverage driven verification. - ... test plans for verification of the full chip or sub- system by working with design engineers and...CPU, NPU, and SOC. - Drive Verification Methodology using System Verilog / C++ based test benches.… more
- Texas Instruments (Dallas, TX)
- …of Analog Mixed Signal products utilizing self checking test benches in System Verilog . + Prior management and/or leadership experience **Preferred ... qualifications:** + Extensive knowledge in Verilog , SystemVerilog, UVM Verification environments with metric...Maestro + Experience writing models for analog circuits and systems , either in Verilog AMS or real… more
- Cadence Design Systems, Inc. (Edinburgh, IN)
- …30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that ... Design Engineering Director Job Overview: The Cadence Computer Systems Group (CSG) develops and licenses IP for ...and interconnects, high-speed interfaces, or chiplets. + Expertise in Verilog / System Verilog for coding and… more
- Qualcomm (Austin, TX)
- …and tools. + Creates and maintains verification test benches and environments in System Verilog / UVM + Create and leverage advanced testing frameworks ... experience + Verification skills: Test planning, Scripting, Simulation, problem solving and debug. + System Verilog , UVM , Verilog or VHDL, C/C++ skills… more
- Texas Instruments (Dallas, TX)
- …related field + 5+ years of Analog Mixed Signal verification experience utilizing System Verilog **Preferred qualifications:** + Experience using Verilog , ... for TI's largest customers. You will work closely with design , systems , characterization, test and product engineers...SystemVerilog, Verilog -A, Verilog -AMS, Python, UVM , Cadence ADE-L/ADE-XL or Maestro + Strong background with… more
- Capgemini (San Francisco, CA)
- …+ Extract modeling specifications from designers + Development of Analog/Mixed-Signal model in System - Verilog + Development of UVM Testbench and developing ... by other groups **Required Skills:** + Good knowledge of System - Verilog RTL coding including state machines, adders,...design for mixed signal control loops and designing Verilog / Verilog - A code to control… more
- Broadcom (Broomfield, CO)
- …evolve rapidly at every generation in a very dynamic market using industry proven methodologies using System Verilog and UVM . You can become a member of an ... of a stable team developing silicon products for Ethernet systems in the Cloud? Come join this team creating... UVM , well versed in OOP_** **_T_** **_ools/Languages: System Verilog (TB structures - Class, SVA,… more