• UVM / SystemVerilog Design…

    US Tech Solutions (Goleta, CA)
    …and AXI to driven the internal components and send data. **Responsibilities** + As a UVM / SystemVerilog Design Verification Engineer, you will own ... **Job Description:** + The project relates to the design and verification of a custom...with verification methodologies and languages such as UVM and SystemVerilog . + Experience developing and… more
    US Tech Solutions (11/08/25)
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  • SystemVerilog / UVM Design…

    US Tech Solutions (Goleta, CA)
    …scripting) - must be able to automate test or regression flows **Skills:** + UVM /System Verilog + Design Verification + Ethernet, SPI, AXI, JTAG ... engineer who can work independently and take ownership of verification deliverables within a UVM / SystemVerilog ...tasks. **Experience:** + 5-8 years of experience in Pre-Silicon Design Verification (FPGA or ASIC). + Strong… more
    US Tech Solutions (10/14/25)
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  • Senior ASIC Verification Engineer - Global…

    NVIDIA (Austin, TX)
    …design verification experience + Experience in pre-silicon verification ( UVM , SystemVerilog ), ASIC design /implementation flow, and design ... components using SV/ UVM methodology + Driving coverage-based verification closure + Collaborate with design teams...the crowd: + Previous experience automating tasks in the design verification process + Hands on experience… more
    NVIDIA (10/16/25)
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  • Senior Engineer ( Verification Engineer)

    Data Device Corporation (Bohemia, NY)
    …inVHDL;working knowledge ofVerilog, SystemVerilog and UVM for function verification . + FPGA Design Tools: Proficiency in Xilinx Vivado required; ... involves developing robust testbenches, creating advanced simulation environments, executing verification suites, and collaborating closely with Design Engineers… more
    Data Device Corporation (11/08/25)
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  • Senior Design Verification Engineer,…

    Google (Mountain View, CA)
    …8 years of experience with verification methodologies and languages such as UVM and SystemVerilog . + Experience developing and maintaining verification ... Senior Design Verification Engineer, Silicon _corporate_fare_ Google...Create and enhance constrained-random verification environments using SystemVerilog and Universal Verification Methodology ( UVM… more
    Google (10/16/25)
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  • Design Verification Engineer

    Meta (Redmond, WA)
    … verification 8. 2+ years experience in block/IP/sub-system and/or SoC level verification based on SystemVerilog UVM /OVM based methodologies 9. Experience ... from transistors, through architecture, firmware, and algorithms. **Required Skills:** Design Verification Engineer Responsibilities: 1. Define and implement… more
    Meta (11/08/25)
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  • ASIC Engineer, Design Verification

    Meta (Sunnyvale, CA)
    … verification 10. 8+ years experience in IP/sub-system and/or SoC level verification based on SystemVerilog UVM /OVM based methodologies 11. Experience ... responsible for the verification closure of a design module or sub-system from test-planning, UVM based test bench development to verification closure.… more
    Meta (10/30/25)
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  • ASIC Engineer, Design Verification

    Meta (Sunnyvale, CA)
    … verification 9. 6+ years of experience in IP/sub-system and/or SoC level verification based on SystemVerilog UVM /OVM based methodologies 10. Experience ... responsible for the verification closure of a design module or sub-system from test-planning, UVM based test bench development to verification closure.… more
    Meta (10/30/25)
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  • Intern - ASIC Design Verification

    Micron Technology, Inc. (Minneapolis, MN)
    …strong foundation in ASIC verification . **Responsibilities** + Work with UVM -based SystemVerilog testbenches to verify ASIC functionality. + Collaborate with ... learn, communicate and advance faster than ever. **Department Introduction** Micron's ASIC Design Verification team ensures the functionality and quality of… more
    Micron Technology, Inc. (09/26/25)
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  • Lead E/E & Semiconductor Engineer - SOC…

    Capgemini (Seattle, WA)
    …Qualifications** + Experience verifying GPU/CPU designs and developing UVM -based verification environments from scratch. + Background in design ... **Job Description:** We are seeking a SoC Design Verification Engineer to join our...+ 8 to 10 years of hands-on experience with SystemVerilog and UVM methodology. + Proficiency in… more
    Capgemini (10/14/25)
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