- US Tech Solutions (Goleta, CA)
- …and AXI to driven the internal components and send data. **Responsibilities** + As a UVM / SystemVerilog Design Verification Engineer, you will own ... **Job Description:** + The project relates to the design and verification of a custom...with verification methodologies and languages such as UVM and SystemVerilog . + Experience developing and… more
- US Tech Solutions (Goleta, CA)
- …scripting) - must be able to automate test or regression flows **Skills:** + UVM /System Verilog + Design Verification + Ethernet, SPI, AXI, JTAG ... engineer who can work independently and take ownership of verification deliverables within a UVM / SystemVerilog ...tasks. **Experience:** + 5-8 years of experience in Pre-Silicon Design Verification (FPGA or ASIC). + Strong… more
- NVIDIA (Austin, TX)
- …design verification experience + Experience in pre-silicon verification ( UVM , SystemVerilog ), ASIC design /implementation flow, and design ... components using SV/ UVM methodology + Driving coverage-based verification closure + Collaborate with design teams...the crowd: + Previous experience automating tasks in the design verification process + Hands on experience… more
- Data Device Corporation (Bohemia, NY)
- …inVHDL;working knowledge ofVerilog, SystemVerilog and UVM for function verification . + FPGA Design Tools: Proficiency in Xilinx Vivado required; ... involves developing robust testbenches, creating advanced simulation environments, executing verification suites, and collaborating closely with Design Engineers… more
- Meta (Sunnyvale, CA)
- … verification 9. 6+ years of experience in IP/sub-system and/or SoC level verification based on SystemVerilog UVM /OVM based methodologies 10. Experience ... from transistors, through architecture, firmware, and algorithms. **Required Skills:** Design Verification Engineer Responsibilities: 1. Define and implement… more
- Meta (Sunnyvale, CA)
- … verification 8. 2+ years experience in block/IP/sub-system and/or SoC level verification based on SystemVerilog UVM /OVM based methodologies 9. Experience ... from transistors, through architecture, firmware, and algorithms. **Required Skills:** Design Verification Engineer Responsibilities: 1. Define and implement… more
- Meta (Sunnyvale, CA)
- … verification 9. 6+ years of experience in IP/sub-system and/or SoC level verification based on SystemVerilog UVM /OVM based methodologies 10. Experience ... responsible for the verification closure of a design module or sub-system from test-planning, UVM based test bench development to verification closure.… more
- Meta (Sunnyvale, CA)
- … verification 8. 2+ years experience in block/IP/sub-system and/or SoC level verification based on SystemVerilog UVM /OVM based methodologies 9. Experience ... responsible for the verification closure of a design module or sub-system from test-planning, UVM based test bench development to verification closure.… more
- Micron Technology, Inc. (Minneapolis, MN)
- …strong foundation in ASIC verification . **Responsibilities** + Work with UVM -based SystemVerilog testbenches to verify ASIC functionality. + Collaborate with ... learn, communicate and advance faster than ever. **Department Introduction** Micron's ASIC Design Verification team ensures the functionality and quality of… more
- Google (Sunnyvale, CA)
- …to identify important verification scenarios. + Create and enhance constrained-random verification environments using SystemVerilog and UVM , or formally ... ASIC Design Verification Engineer, University Graduate _corporate_fare_...SystemVerilog for ASICs. + Experience in power aware verification , gate level simulations, and post silicon bring-up. +… more