- Google (Mountain View, CA)
- …field, or equivalent practical experience. + 5 years of experience with digital logic design principles, RTL design concepts, and languages such as Verilog ... SystemVerilog. + Experience with logic synthesis techniques to optimize RTL code, performance and power as well as low-power... code, performance and power as well as low-power design techniques. Preferred qualifications: + Master's degree or PhD… more
- Google (Sunnyvale, CA)
- …development of silicon-based ICs and chips. + Experience in verifying digital logic at RTL using SystemVerilog for ASICs. + Experience in memory subsystem design ... AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML… more
- Google (Sunnyvale, CA)
- … architecture and its integration within AI/ML-driven systems. As a Custom Datapath Physical Design Engineer on the Chip Implementation team, you will work on ... acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most...ROI-based recommendations to the project. + Work closely with RTL designers and inform design decisions to… more
- Google (Madison, WI)
- …on TPU architecture and its integration within AI/ML-driven systems. As an ASIC Design Verification Engineer , you will use your design and verification ... equivalent practical experience. + Experience in verifying digital logic at RTL using SystemVerilog for ASICs. Preferred qualifications: + Experience with… more
- Google (Sunnyvale, CA)
- …of hardware experiences, delivering unparalleled performance, efficiency, and integration. As part of the TPU Power Design team, you will play a pivotal part in ... practical experience. + 3 years of experience in ASIC design or equivalent practical experience. + Experience in chip...building or maintaining automated tool flows. + Proficiency in RTL languages such as SystemVerilog. Be part of a… more